HPC46100 datasheet(5/32 Pages) NSC

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40 MHz (Continued)

AC Electrical Characteristics (Continued)

See Notes 1 and 4 and

Figure 1 thru Figure 5 VCC e 50V g10% unless otherwise specified TA e 25 C one wait state

Symbol

Parameter

Min

Max

Units

E SIGNAL TIMING PARAMETERS

tRWSE e 025 tC b 7WR Falling Edge to E Rising Edge

tRWHE e 05 tC b 7

E Falling Edge to WR Rising Edge

tASE e tC b 20

Address Valid to E Rising Edge

tRDE e WS b 20

E Falling Edge to Data Input Valid

SLOW PERIPHERAL TIMING PARAMETERS

tPLL e tC b 5

PALE Pulse Width

tPST e 075 tC b 10

Address Valid to PALE Falling Edge

275

tPVL e 075 tC b 15

Address Hold from PALE Falling Edge

225

tPVP e 075 tC b 10

PALE Falling Edge to RD or WR Falling Edge

275

tPCSA e 025 tC b 125

Chip Select Setup to PALE Falling Edge

tPAS e 15 tC b 20

Address Setup to RD or WR Falling Edge

tPCSS e tC b 15

Chip Select Setup to RD or WR Falling Edge

tPCSH e 05 tC b 15

Chip Select Hold from RD or WR Rising Edge

tPACC e 5tC b 25

Address Valid to Input Data Valid

225

tPRD e 35 tC b 25

RD Falling Edge to Data In Valid

150

tPDR e tC (max)

Data Hold after RD Rising Edge

tPRW e 35 tC b 15

RD Strobe Width

160

tPSW e 30 tC b 20

Data Setup before WR Rising Edge

130

tPHW e tC b 20

Data Hold after WR Rising Edge

tPWW e 35 tC b 15

WR Strobe Width

160

Note

CL e 40 pF

Note 1

These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall

times (tCKIR and tCKIL) on CKI input less than 25 ns

Note 2

Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either

CKI or CKO is connected to any external logic other than the passive components of the crystal circuit

Note 3

tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle begin executed If HLD falling

edge occurs later tHAE as long as (3 tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait states and ready input

Note 4

WS (tWAIT) x (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency tC e 40 MHz with

one wait state programmed

Note 5

Due to testing limitationsactual limits will be better

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