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AD7927

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The Timer register, for instance, is loaded with a value that will

provide an interrupt at the required sample interval. When an

interrupt is received, a value is transmitted with TFS/DT (ADC

control word). The TFS is used to control the RFS and therefore

the reading of data. The frequency of the serial clock is set in the

SCLKDIV Register. When the instruction to transmit with TFS

is given (i.e., AX0 = TX0), the state of the SCLK is checked.

The DSP will wait until the SCLK has gone High, Low, and

High before transmission will start. If the timer and SCLK values

are chosen such that the instruction to transmit occurs on or

near the rising edge of SCLK, then the data may be transmitted

or it may wait until the next clock edge.

For example, if the ADSP-2189 had a 20 MHz crystal such that

it had a master clock frequency of 40 MHz, then the master cycle

time would be 25 ns. If the SCLKDIV Register is loaded with the

value 3, then an SCLK of 5 MHz is obtained and eight master

clock periods will elapse for every one SCLK period. Depending

on the throughput rate selected, if the Timer Registers are loaded

with the value, say 803, 100.5 SCLKs will occur between inter-

rupts and subsequently between transmit instructions. This

situation will result in non-equidistant sampling as the transmit

instruction is occurring on a SCLK edge. If the number of

SCLKs between interrupts is a whole integer figure of N, then

equidistant sampling will be implemented by the DSP.

AD7927 to DSP563xx

The connection diagram in Figure 22 shows how the AD7927

can be connected to the ESSI (Synchronous Serial Interface) of

the DSP563xx family of DSPs from Motorola. Each ESSI (two on

board) is operated in Synchronous mode (SYN bit in CRB = 1)

with internally generated word length frame sync for both Tx

and Rx (bits FSL1 = 0 and FSL0 = 0 in CRB). Normal operation

of the ESSI is selected by making MOD = 0 in the CRB. Set the

word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA.

The FSP bit in the CRB should be set to 1 so the frame sync is

negative. It should be noted that for signal processing applica-

tions, it is imperative that the frame synchronization signal from

the DSP563xx provides equidistant sampling.

In the example shown in Figure 22, the serial clock is taken from

the ESSI so the SCK0 pin must be set as an output, SCKD = 1.

The VDRIVE pin of the AD7927 takes the same supply voltage as

that of the DSP563xx. This allows the ADC to operate at a higher

voltage than the serial interface, i.e., DSP563xx, if necessary.

AD7927*

DSP563xx*

SCK

SRD

STD

SC2

VDD

SCLK

DOUT

DIN

VDRIVE

*ADDITIONAL PINS REMOVED FOR CLARITY

Figure 22. Interfacing to the DSP563xx

APPLICATION HINTS

Grounding and Layout

The AD7927 has very good immunity to noise on the power

supplies as can be seen by the PSRR vs. Supply Ripple Frequency

plot, TPC 3. However, care should still be taken with regard to

grounding and layout.

The printed circuit board that houses the AD7927 should be

designed such that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the use

of ground planes that can be separated easily. A minimum etch

technique is generally best for ground planes as it gives the best

shielding. All three AGND pins of the AD7927 should be sunk

in the AGND plane. Digital and analog ground planes should be

joined at only one place. If the AD7927 is in a system where

multiple devices require an AGND to DGND connection, the

connection should still be made at one point only, a star ground

point that should be established as close as possible to the AD7927.

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed to

run under the AD7927 to avoid noise coupling. The power supply

lines to the AD7927 should use as large a trace as possible to

provide low impedance paths and reduce the effects of glitches

on the power supply line. Fast switching signals, like clocks,

should be shielded with digital ground to avoid radiating noise

to other sections of the board, and clock signals should never be

run near the analog inputs. Avoid crossover of digital and analog

signals. Traces on opposite sides of the board should run at right

angles to each other. This will reduce the effects of feedthrough

through the board. A microstrip technique is by far the best but

is not always possible with a double-sided board. In this technique,

the component side of the board is dedicated to ground planes

while signals are placed on the solder side.

Good decoupling is also important. All analog supplies should be

decoupled with 10

mF tantalum in parallel with 0.1 mF capacitors

to AGND. To achieve the best from these decoupling components,

they must be placed as close as possible to the device, ideally

right up against the device. The 0.1

mF capacitors should have

low Effective Series Resistance (ESR) and Effective Series Induc-

tance (ESI), such as the common ceramic types or surface mount

types, which provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switching.

Evaluating the AD7927 Performance

The recommended layout for the AD7927 is outlined in the

evaluation board for the AD7927. The evaluation board package

includes a fully assembled and tested evaluation board, docu-

mentation, and software for controlling the board from the

PC via the Eval-Board Controller. The Eval-Board Controller

can be used in conjunction with the AD7927 Evaluation board

as well as many other Analog Devices evaluation boards ending

in the CB designator to demonstrate/evaluate the ac and dc

performance of the AD7927.

The software allows the user to perform ac (fast Fourier

transform) and dc (histogram of codes) tests on the AD7927.

The software and documentation are on a CD shipped with the

evaluation board.

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