DS1WM

7 of 15

first byte

7

6

5

43

21

0

et cetera

7

6

5

43

21

0

In this scheme, the index (values from 0 to 63, “n”) designates the position of the bit in the ROM ID of a

1-Wire device. The character “x” marks bits that act as a filler and do not require a specific value (don’t

care bits). The character “r” specifies the selected bit value to write at that particular bit in case of a

conflict during the execution of the ROM search.

For each bit position n (values from 0 to 63) the 1-Wire Master will generate three time slots on the 1-

Wire bus. These are referenced as:

b0

for the first time slot (read data)

b1

for the second time slot (read data) and

b2

for the third time slot (write data).

The 1-Wire Master determines the type of time slot b2 (write 1 or write 0) as follows:

b2

= 1 if error (there is no response)

The response bytes that will be in the Data Register for the CPU to read during a complete pass through a

Search ROM function using the Search Accelerator consists of 16 bytes as follows:

first byte

7

6

5

43

21

0

et cetera

7

6

5

43

21

0

As before, the index designates the position of the bit in the ROM ID of a 1-Wire device. The character

“d” marks the discrepancy flag in that particular bit position. The discrepancy flag will be 1 if there is a

conflict or no response in that particular bit position and 0 otherwise. The character “r’” marks the

actually chosen path at that particular bit position. The chosen path is identical to b2 for the particular bit

position of the ROM ID.