DS1WM

8 of 15

been found and addressed. When the Search ROM process is complete the SRA bit should be cleared in

order to release the 1-Wire Master from Search ROM Accelerator Mode.

is repeated until the highest discrepancy occurs in the same bit position for two consecutive passes.

EXAMPLE — ACCELERATED ROM SEARCH

In this example, the host will use the 1-Wire Master to identify four different devices on the 1-Wire bus.

The ROM data of the devices is as shown (LSB first):

ROM1 = 00110101…

ROM2 = 10101010…

ROM3 = 11110101…

ROM4 = 00010001…

1) The host issues a reset pulse by writing 0x01h to the Command Register. All slave devices respond

simultaneously with a presence detect.

2) The host issues a Search ROM command by writing 0xF0h to the Transmit Buffer.

3) The host places the 1-Wire Master in Accelerator mode by writing 0x02 to the Command Register.

4) The host writes 0x00h to Transmit Buffer and reads the returning data from the Receive Buffer. This

process is repeated for a total of 16 bytes. The data read will contain ROM4 in the r’ locations and

discrepancy bits set at d0 and d2 as shown (r’ locations are underlined, most significant discrepancy is

bolded ):

RECEIVED DATA 1 =

1000100100000001….

5) The host then de-interleaves the data to arrive at a ROM code of 00010001… with the last

discrepancy at location d2.

6) The host writes 0x00h to the Command Register to exit Search Accelerator mode. The host is now

free to send a command or read data directly from this device.

7) Steps 1-6 are now repeated to find the next device. The 16 bytes of data transmitted this time are

identical to ROM4 up until the last discrepancy bit (d2 in this case) which is inverted and all data

following is set to 0 as shown. The received data will contain ROM1 in the r’ locations and bits d0

and d2 will be set again:

TRANSMITTED DATA 2 = 0000010000000000…

RECEIVED DATA 2 =

1000110100010001…

8) Since the most significant discrepancy (d2) did not change, the next most (d0) will be used and the

process repeats. Further iterations contain the data as shown:

TRANSMITTED DATA 3 = 0100000000000000…

RECEIVED DATA 3 =

1110010001000100…

TRANSMITTED DATA 4 = 0101000000000000…

RECEIVED DATA 4 =

1111010100010001…