DS1WM datasheet(11/15 Pages) DALLAS

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DS1WM

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I/0 SIGNALING

The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by

the 1-Wire Master are the initialization sequence (Reset Pulse followed by Presence Pulse), Write 0,

Write 1, and Read Data. The master initiates all of these types of signaling except the Presence Pulse.

The initialization sequence required to begin any communication with the bus slave is shown in Figure

1. A Presence Pulse following a Reset Pulse indicates the slave is ready to accept a ROM Command.

The 1-Wire Master transmits a reset pulse for tRSTL. The 1-Wire bus line is then pulled high by the pull-

up resistor. After detecting the rising edge on the DQ pin, the slave waits for tPDH and then transmits the

Presence Pulse for tPDL. The master samples the bus at tPDS after the slave responds to test for a valid

presence pulse. The result of this sample is stored in the PDR bit of the Interrupt Register. The reset time

slot ends tRSTH after the master releases the bus.

1-WIRE INITIALIZATION SEQUENCE (RESET PULSE AND PRESENCE

PULSE) Figure 1

WRITE TIME SLOTS

A write time slot is initiated when the 1-Wire Master pulls the 1-Wire bus line from a logic high

(inactive) level to a logic low level. The master generates a Write 1 time slot by releasing the line at tLOW1

and allowing the line to pull up to a logic high level. The line is held low for tLOW0 to generate a Write 0

time slot. A slave device will sample the 1-Wire bus line between 15µs and 60ms (between 2µs and 6ms in

Overdrive mode) after the line falls. If the line is high when sampled, a Write 1 occurs. If the line is low

when sampled, a Write 0 occurs (see Figure 2).

READ TIME SLOTS

A read time slot is initiated when the 1-Wire Master pulls the bus low for at least 1 ms and then releases it.

If the slave device is responding with a 0 it will continue to hold the line low for up to 60

ms (6ms in

Overdrive mode), otherwise it will release it immediately. The master will sample the data tRDV from the

start of the read time slot. The master will end the read slot after a time of tSLOT. See Figure 2 for more

information.

LINE TYPE LEGEND:

1-Wire Master active low

Slave device active low

Resistor pullup

Both Master and

Slave device active low

tRSTL

tPDL

tRSTH

tPDH

VCC

GND

tPDS

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