DS1WM

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PIN DESCRIPTIONS

The following describes the function of all the block I/O pins. In the following descriptions, 0 represents

logic low and 1 represents logic high.

A0, A1, A2, Register Select: Address signals connected to these three inputs select a register for the CPU

to read from or write to during data transfer. A table of registers and their addresses is shown below.

Register Addresses

A2

A1

A0

Register

0

0

0

Command Register (read/write)

0

0

1

Transmit Buffer (write), Receive Buffer (read)

0

1

0

Interrupt Register (read)

0

1

1

Interrupt Enable Register (read/write)

1

0

0

Clock Divisor Register (read/write)

ADS , Address Strobe: The positive edge of an active Address Strobe (ADS ) signal latches the Register

Select (A0, A1, A2) into an internal latch. Provided that setup and hold timings are observed,

ADS may

be tied low making the latch transparent.

CLK, Clock Input: This is a (preferably) 50% duty cycle clock that can range from 3.2MHz to 128MHz.

This clock provides the timing for the 1-Wire bus.

D7-D0, Data Bus: This bus comprises eight input/output lines. The bus provides bi-directional

communications between the 1-Wire Master and the CPU. Data, control words, and status information are

transferred via this D7-D0 Data Bus.

DQ, 1-Wire Data Line: This open-drain line is the 1-Wire bi-directional data bus. 1-Wire slave devices

are connected to this pin. This pin must be pulled high by an external resistor, nominally 5K

W.

EN , Enable: When EN is low, the 1-Wire Master is enabled; this signal acts as the device chip enable.

This enables communication between the 1-Wire Master and the CPU.

INTR, Interrupt: This line goes to its active state whenever any one of the interrupt types has an active

high condition and is enabled via the Interrupt Enable Register. The INTR signal is reset to an inactive

state when the Interrupt Register is read.

MR, Master Reset: When this input is high, it clears all the registers and the control logic of the 1-Wire

Master, and sets INTR to its default inactive state, which is HIGH.

RD

, Read: This pin drives the bus during a read cycle. When the circuit is enabled, the CPU can read

low simultaneously; if they are, WR takes precedence.

WR , Write: This pin drives the bus during a write cycle. When WR is low while the circuit is enabled,

simultaneously; if they are, WR takes precedence.