DS1WM

9 of 15

9) At this point, the most significant discrepancy (d1) did not change so the next most (d0) should be

used. However, d0 has now been reached for the second time and since there are no less significant

discrepancies, the search is complete having found a total of four devices.

OPERATION — FLAGS AND INTERRUPTS

Flags from transmit, receive, and 1-Wire reset operations are located in the Interrupt Register. Only the

Presence Detect flag (PD) is cleared when the Interrupt Register is read, the other flags are cleared

automatically when written to or read from the transmit and receive buffers. These flags can generate an

interrupt on the INTR pin if the corresponding enable bit is set in the Interrupt Enable Register. Reading

the Interrupt Register always sets the INTR pin inactive even if all flags are not cleared.

Interrupt Register (Read-Only)

Addr. 02h

DQI

NBSY

SINT

RBF

TEMT

TBE

PDR

PD

MSB

LSB

PD: Presence Detect. After a 1-Wire Reset has been issued, this flag will be set after the appropriate

amount of time for a presence detect pulse to have occurred. The default state for this bit is 0. This bit is

cleared when the Interrupt Register is read.

PDR: Presence Detect Result. When a Presence Detect interrupt occurs, this bit will reflect the result of

the presence detect read; it will be 0 if a slave device was found, or 1 if no parts were found. The default

state for this bit is 1.

TBE: Transmit Buffer Empty. This flag will be cleared when data is written to the Transmit Buffer and

cleared when that data is transferred to the Transmit Shift Register. The default state for this bit is 1.

TEMT: Transmit Shift Register Empty. This flag will be cleared when data is shifted into the Transmit

Shift Register from the Transmit Buffer and set after the last bit has been transmitted on the 1-Wire bus.

The default state for this bit is 1.

RBF: Receive Buffer Full. This flag will be set when there is a byte waiting to be read in the Receive

Buffer. This flag will be cleared when the byte is read from the Receive Buffer Register. The default state

for this bit is 0.

SINT: Slave Interrupt. This flag is set when the 1-Wire bus is held low by a slave device for a period of

greater than 960us. This bit is cleared when the register is read. The default state for this bit is 0.

NBSY: Not Busy. The default state for this bit is 1 indicating that no operation is currently taking place

inside the 1-Wire Master. It is cleared whenever a read, write, reset, or slave interrupt takes place. When

the operation ends this flag returns to a 1 state.

DQI: DQ Input. This bit is a mirror of bit 3 in the Command Register. This allows the entire status of the

master and the bus to be determined by reading only the Interrupt Register. This bit does not have a

corresponding enable bit in the Interrupt Enable Register.

The Interrupt Enable Register allows the system programmer to specify the source of interrupts, which

will cause the INTR pin to be active, and to define the active state for the INTR pin. When a Master Reset

is received all bits in this register are cleared to 0 disabling all interrupt sources and setting the active

state of the INTR pin to LOW. This means the INTR pin will be pulled high since all interrupts are

disabled. The INTR pin is reset to an inactive state by reading the Interrupt Register.