DS1WM

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OPERATION – CLOCK DIVISOR

All 1-Wire timing patterns are generated using a base clock of 1.0MHz. The 1-Wire Master will generate

this clock frequency internally given an external reference on the CLK pin. The external clock must have

a frequency from 3.2MHz to 128MHz and a 50% duty cycle is preferred. The Clock Divisor Register

controls the internal clock divider and provides the desired reference frequency. This is done in two

stages: first a prescaler divides by 1, 3, 5, or 7, then the remaining circuitry divides by 2, 4, 8, 16, 32,

64,or 128.

Clock Divisor Register

Addr. 04h

X

X

X

DIV2

DIV1

DIV0

PRE1

PRE0

MSB

LSB

The clock divisor must be configured before communication on the 1-Wire bus can take place. This

register is set to 0x00h if a Master Reset occurs. Use the table below to find the proper register value

based on the CLK reference frequency. For example, the user would write 0x10h to this location when

providing a 15MHz input clock.

Clock Divisor Register Settings for Input Clock Rates

Min CLK

Frequency

(MHz)

Max CLK

Frequency

(MHz)

Divider

Ratio

DIV3

DIV2

DIV1

PRE1

PRE0

>3.2

4.0

4

0

1000

>4.0

5.0

5

0

0010

>5.0

6.0

6

0

0101

>6.0

7.0

7

0

0011

>7.0

8.0

8

0

1100

>8.0

10.0

10

0

0110

>10.0

12.0

12

0

1001

>12.0

14.0

14

0

0111

>14.0

16.0

16

1

0000

>16.0

20.0

20

0

1010

>20.0

24.0

24

0

1101

>24.0

28.0

28

0

1011

>28.0

32.0

32

1

0100

>32.0

40.0

40

0

1110

>40.0

48.0

48

1

0001

>48.0

56.0

56

0

1111

>56.0

64.0

64

1

1000

>64.0

80.0

80

1

0010

>80.0

96.0

96

1

0101

>96.0

112.0

112

1

0011

>112.0

128.0

128

1

1100