EC-1 datasheet(4/58 Pages) RENESAS

4 / 58 page

R01DS0289EJ0100 Rev.1.00

Page 4 of 58

Sep 30, 2016

EC-1

1. Overview

Note 1. EtherCAT is a registered trademark of Beckhoff Automation GmbH, Germany.

Note 2. Channels 3 and 4 are used only in asynchronous mode.

Note 3. When the operating temperature (junction temperature) is 110°C or higher, refer to the precautions regarding the high-

temperature operation on the EC-1(R01AN3998).

Communication

function

Serial peripheral

interface (RSPIa)

• 2 channels

• RSPI transfer facility

Using the MOSI (master out slave in), MISO (master in slave out), SSL (slave select),

and RSPCK (RSPI clock) signals enables serial transfer through SPI operation (four

lines) or clock-synchronous operation (three lines)

Capable of handling serial transfer as a master or slave

• Data formats

Switching between MSB first and LSB first

The number of bits in each transfer can be changed to any number of bits from 8 to 16,

or 20, 24, or 32 bits.

128-bit buffers for transmission and reception

Up to four frames can be transmitted or received in a single transfer operation (with

each frame having up to 32 bits)

• Buffered structure

Double buffers for both transmission and reception

• RSPCK can be stopped automatically with the receive buffer full for master reception

• Event linking by the ELC

SPI multi I/O bus

controller (SPIBSC)

• 1 channel

• One serial flash memory with multiple I/O bus sizes (single/dual/quad) can be

connected.

• External address space read mode (built-in read cache)

• SPI operating mode

• Clock polarity and clock phase can be selected.

• Maximum transfer rate: 300 Mbps (for quad)

Safety

function

Protects important registers from being overwritten for in case a program runs out of

control.

CRC calculator (CRC)

• CRC code generation for arbitrary amounts of data in 8-, 16-, or 32-bit units

• Select any of four generating polynomials:

X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 (32-

Ethernet),

X16 + X12 + X5 + 1 (16-CCITT),

X8 + X4 + X3 + X2 + 1 (8-SAEJ1850),

X8 + X5 + X3 + X2 + X + 1 (8-0x2F)

Input clock oscillation

stop function

Input clock oscillation stop detection: Available

Clock monitor circuit

(CLMA)

Monitors the abnormal output clock frequency from the PLL circuit or low-speed on-chip

oscillator.

Error control module

(ECM)

• Generates an interrupt, internal reset, or error output for the error signal input from each

module.

• Time-out function

• The error control is duplicated in the master and the checker.

Power supply voltage

VDD = PLLVDD0 = PLLVDD1 = DVDD_USB = 1.14 to 1.26 V

VCCQ33 = VDD33_USB = 3.0 to 3.6 V

Operating temperature*3

Tj = -40 to +125°C

Package

196-pin FBGA: 12 × 12 mm, 0.8-mm pitch PLBG0196GA-B

Debugging interface

• CoreSight architecture designed by ARM

• Debugging function by the JTAG/SWD interface, and trace function by the trace port/

SWV interface

Table 1.1

Outline of Specifications (3 / 3)

Classification

Module/Function

Description

EC-1 Datasheet(PDF) 4 Page - Renesas Technology Corp

EC-1 Datasheet(HTML) 4 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL