EC-1 datasheet(3/58 Pages) RENESAS

3 / 58 page

R01DS0289EJ0100 Rev.1.00

Page 3 of 58

Sep 30, 2016

EC-1

1. Overview

Event link controller (ELC)

• Event signals can be interlinked with the operation of modules.

• In particular, the operation of timer modules can be started by input event signals.

• Event-linked operation of signals of ports B and E is to be possible.

Multi-function pin controller (MPC)

The locations of input/output functions are selectable from among multiple pins.

Timer

Compare match timer

(CMT)

• (16 bits × 2 channels) × 3 units

• Select from among four counter-input clock signals for each channel (with maximum

operating frequency of 75 MHz)

• Event linking by the ELC

Compare match timer W

(CMTW)

• (32 bits × 1 channel) × 2 units

• Compare-match, input-capture input, and output-comparison output are available.

• Select from among four counter-input clock signals for each channel (with maximum

operating frequency of 75 MHz)

• Interrupt requests can be output in response to compare-match, input-capture, and

output-comparison events.

• Digital noise filter function for signals on the input capture pins

• Event linking by the ELC

Watchdog timer (WDTA)

• 14 bits × 1 channel

• Select from among six counter-input clock signals for each channel (with maximum

operating frequency of 75 MHz)

Independent watchdog

timer (IWDTa)

• 14 bits × 1 channel

• Counter-input clock: Low-speed on-chip oscillator (LOCO)/2

Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64,

dedicated clock/128, dedicated clock/256 (with maximum operating frequency of 120

MHz)

Communication

function

EtherCAT Slave

Controller (ESC) *1

• 1 channel (2 ports)

• EtherCAT Slave Controller IP core (made by Beckhoff Automation GmbH) implemented

USB 2.0 HS host/

function module

• 1 port

• Compliance with the USB 2.0 specification

• Transfer rate

High speed (480 Mbps), full speed (12 Mbps)

• Communications buffer

Incorporates 1 Kbyte of RAM for host mode

Incorporates 8 Kbytes of RAM for function mode

Serial communication

interface with FIFO

(SCIFA)

• 5 channels

• Serial communications modes: Asynchronous, clock synchronous*2

• On-chip baud rate generator allows selection of the desired bit rate

• Choice of LSB-first or MSB-first transfer

• Both the transmission and reception sections are equipped with 16-byte FIFO buffers,

allowing continuous transmission and reception.

• Bit rate modulation

I2C bus interface (RIICa)

• 1 channel

I2C bus format

Supports the multi-master

Max. transfer rate: 400 kbps

• Event linking by the ELC

CAN module (RSCAN)

• 1 channel

• Compliance with the ISO11898-1 specification (standard frame and extended frame)

• Message buffers

Max. 64 x 1 channel of receive message buffers

16 transmit message buffers per channel

• Max. transfer rate: 1 Mbps

Table 1.1

Outline of Specifications (2 / 3)

Classification

Module/Function

Description

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