EC-1 datasheet(7/58 Pages) RENESAS

7 / 58 page

R01DS0289EJ0100 Rev.1.00

Page 7 of 58

Sep 30, 2016

EC-1

1. Overview

1.3

Block Diagram

Figure 1.1 shows a block diagram of a 196-pin device.

ESC:

EtherCAT slave controller

DMACAa:

DMA controller

SPIBSC:

SPI multi I/O bus controller

WDTA:

Watchdog timer

IWDTa:

Independent watchdog timer

SCIFA:

Serial communication interface with FIFO

RSPIa:

Serial peripheral interface

USB:

USB 2.0 HS host/function module

CMT:

Compare match timer

CMTW:

Compare match timer W

RIICa:

I2C bus interface

RSCAN:

CAN module

CRC:

CRC (cyclic redundancy check) calculator

CLMA:

Clock monitor circuit

ECM:

Error control module

VIC:

Vector interrupt controller

MPU:

Memory protection unit

ELC:

Event link controller

Note: Channels 3 and 4 are used only in asynchronous mode.

Figure 1.1

Block Diagram

CMT × 2 channels (unit 1)

CMTW × 1 channel (unit 1)

CMTW × 1 channel (unit 0)

CMT × 2 channels (unit 2)

Clock

generation

circuit

Cortex-R4F

WDTA×1ch

RIIC × 1 channel

CRC

IWDTa

USB

× 1 port

RSCAN × 1 channel

CMT × 2 channels (unit 0)

RSPIa × 2 channels

DMACAa ×

16 channels

(unit 0)

MPU

SCIFA × 5 channels*

ESC

CLMA

VIC

TCM

DMACAa ×

16 channels

(unit 1)

ELC

ECM

SPIBSC

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port A

Port B

Port C

Port D

Port E

Port F

Port G

Port J

Port M

Port R

Port S

Port U

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