LM5145 datasheet(4/67 Pages) TI1

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BST

PGND

VCC

SS/TRK

COMP

AGND

SYNCOUT

SYNCIN

Exposed

Pad

(EP)

LM5145

SNVSAI4 – JUNE 2017

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(1)

P = Power, G = Ground, I = Input, O = Output.

6 Pin Configuration and Functions

RGY Package

20-Pin VQFN With Wettable Flanks

Top View

Connect Exposed Pad on bottom to AGND and PGND on the PCB.

Pin Functions

TYPE(1)

DESCRIPTION

NO.

NAME

EN/UVLO

Enable input and undervoltage lockout programming pin. If the EN/UVLO voltage is below 0.4 V, the

controller is in the shutdown mode with all functions disabled. If the EN/UVLO voltage is greater than 0.4 V

and less than 1.2 V, the regulator is in standby mode with the VCC regulator operational, the SS pin

grounded, and no switching at the HO and LO outputs. If the EN/UVLO voltage is above 1.2 V, the SS/TRK

pin is allowed to ramp and pulse-width modulated gate drive signals are delivered to the HO and LO pins. A

10-μA current source is enabled when EN/UVLO exceeds 1.2 V and flows through the external UVLO

resistor divider to provide hysteresis. Hysteresis can be adjusted by varying the resistance of the external

divider.

Oscillator frequency adjust pin. The internal oscillator is programmed with a single resistor between RT and

the AGND. The recommended maximum oscillator frequency is 1 MHz. An RT pin resistor is required even

when using the SYNCIN pin to synchronize to an external clock.

SS/TRK

Soft-start and voltage tracking pin. An external capacitor and an internal 10-μA current source set the ramp

rate of the error amplifier reference during start-up. When the SS/TRK pin voltage is less than 0.8 V, the

SS/TRK voltage controls the noninverting input of the error amp. When the SS/TRK voltage exceeds 0.8 V,

the amplifier is controlled by the internal 0.8-V reference. SS/TRK is discharged to ground during standby

and fault conditions. After start-up, the SS/TRK voltage is clamped 115 mV above the FB pin voltage. If FB

falls due to a load fault, SS/TRK is discharged to a level 115 mV above FB to provide a controlled recovery

when the fault is removed. Voltage tracking can be implemented by connecting a low impedance reference

between 0 V and 0.8 V to the SS/TRK pin. The 10-µA SS/TRK charging current flows into the reference

and produces a voltage error if the impedance is not low. Connect a minimum capacitance from SS/TRK to

AGND of 2.2 nF.

COMP

Low impedance output of the internal error amplifier. The loop compensation network should be connected

between the COMP pin and the FB pin.

Feedback connection to the inverting input of the internal error amplifier. A resistor divider from the output

to this pin sets the output voltage level. The regulation threshold at the FB pin is nominally 0.8 V.

LM5145 Datasheet(PDF) 4 Page - Texas Instruments

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