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LM5145 Datasheet(PDF) 8 Page - Texas Instruments |
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LM5145 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 67 page  8 LM5145 SNVSAI4 – JUNE 2017 www.ti.com Product Folder Links: LM5145 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Electrical Characteristics (continued) Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature range unless otherwise stated. VIN = 48 V, VEN/UVLO = 1.5 V, RRT = 25 kΩ unless otherwise stated. (1)(2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVCC-EXT Minimum external bias supply voltage Voltage required to disable VCC regulator 8 V IVCC External VCC input current, not switching VSS/TRK = 0 V, VVCC = 13 V 2.1 mA ENABLE AND INPUT UVLO VSDN Shutdown to standby threshold VEN/UVLO rising 0.42 V VSDN-HYS Shutdown threshold hysteresis EN/UVLO rising – falling threshold 50 mV VEN Standby to operating threshold VEN/UVLO rising 1.164 1.2 1.236 V IEN-HYS Standby to operating hysteresis current VEN/UVLO = 1.5 V 9 10 11 µA ERROR AMPLIFIER VREF FB reference voltage FB connected to COMP 792 800 808 mV IFB-BIAS FB input bias current VFB = 0.8 V –0.1 0.1 µA VCOMP-OH COMP output high voltage VFB = 0 V, COMP sourcing 1 mA 5 V VCOMP-OL COMP output low voltage COMP sinking 1 mA 0.3 V AVOL DC gain 94 dB GBW Unity gain bandwidth 6.5 MHz SOFT START AND VOLTAGE TRACKING ISS SS/TRK capacitor charging current VSS/TRK = 0 V 8.5 10 12 µA RSS SS/TRK discharge FET resistance VEN/UVLO = 1 V, VSS/TRK = 0.1 V 11 Ω VSS-FB SS/TRK to FB offset –15 15 mV VSS-CLAMP SS/TRK clamp voltage VSS/TRK – VFB, VFB = 0.8 V 115 mV POWER GOOD INDICATOR PGUTH FB upper threshold for PGOOD high to low % of VREF, VFB rising 106% 108% 110% PGLTH FB lower threshold for PGOOD high to low % of VREF, VFB falling 90% 92% 94% PGHYS_U PGOOD upper threshold hysteresis % of VREF 3% PGHYS_L PGOOD lower threshold hysteresis % of VREF 2% TPG-RISE PGOOD rising filter FB to PGOOD rising edge 25 µs TPG-FALL PGOOD falling filter FB to PGOOD falling edge 25 µs VPG-OL PGOOD low state output voltage VFB = 0.9 V, IPGOOD = 2 mA 150 mV IPG-OH PGOOD high state leakage current VFB = 0.8 V, VPGOOD = 13 V 100 nA OSCILLATOR FSW1 Oscillator Frequency – 1 RRT = 100 kΩ 100 kHz FSW2 Oscillator Frequency – 2 RRT = 25 kΩ 380 400 420 kHz FSW3 Oscillator Frequency – 3 RRT = 12.5 kΩ 780 kHz SYNCHRONIZATION INPUT AND OUTPUT FSYNC SYNCIN external clock frequency range % of nominal frequency set by RRT –20% +50% VSYNC-IH Minimum SYNCIN input logic high 2 V VSYNC-IL Maximum SYNCIN input logic low 0.8 V RSYNCIN SYNCIN input resistance VSYNCIN = 3 V 20 kΩ TSYNCI-PW SYNCIN input minimum pulsewidth Minimum high state or low state duration 50 ns VSYNCO-OH SYNCOUT high state output voltage ISYNCOUT = –1 mA (sourcing) 3 V VSYNCO-OL SYNCOUT low state output voltage ISYNCOUT = 1 mA (sinking) 0.4 V TSYNCOUT Delay from HO rising to SYNCOUT leading edge VSYNCIN = 0 V, TS = 1/FSW, FSW set by RRT TS/2 – 140 ns |
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