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HT45F5Q Datasheet(PDF) 77 Page - Holtek Semiconductor Inc |
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HT45F5Q Datasheet(HTML) 77 Page - Holtek Semiconductor Inc |
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77 / 114 page  Rev. 1.10 7� De�e��e� 1�� �01� Rev. 1.10 77 De�e��e� 1�� �01� HT45F5Q Charger Flash MCU HT45F5Q Charger Flash MCU A/D Converter Input Signal AlloftheA/Danaloginputpinsarepin-sharedwiththeI/OpinsonPortAaswellasotherfunctions. ThecorredpondingselectionbitsforeachI/OpininthePASRregister,determinewhethertheinput pinsaresetupasA/Dconverteranaloginputsorwhethertheyhaveotherfunctions.Ifthepin-shared functioncontrolbitsconfigureitscorrespondingpinasanA/Danalogchannelinput,thepinwill besetuptobeanA/Dconverterexternalchannelinputandtheoriginalpinfunctionsdisabled.In thisway,pinscanbechangedunderprogramcontroltochangetheirfunctionbetweenA/Dinputs andotherfunctions.Allpull-highresistors,whicharesetupthroughregisterprogramming,willbe automaticallydisconnectedifthepinsaresetupasA/Dinputs.Notethatitisnotnecessarytofirst setuptheA/DpinasaninputinthePACportcontrolregistertoenabletheA/Dinputaswhenthe pin-sharedfunctioncontrolbitsenableanA/Dinput,thestatusoftheportcontrolregisterwillbe overridden. TheA/Dconverterhasitsownreferencevoltagepin,VREF,howeverthereferencevoltagecan alsobesuppliedfromthepowersupplypin,achoicewhichismadethroughtheSAVRS[1:0]inthe SADC1register.TheanaloginputvaluesmustnotbeallowedtoexceedthevalueofVREF. Conversion Rate and Timing Diagram AcompleteA/Dconversioncontainstwoparts,datasamplinganddataconversion.Thedata samplingwhichisdefinedastADStakes4A/Dclockcyclesandthedataconversiontakes12A/D clockcycles.Thereforeatotalof16A/DclockcyclesforanA/DconversionwhichisdefinedastADC arenecessary. MaximumsingleA/Dconversionrate=A/Dclockperiod/16 However,thereisausagelimitationonthenextA/Dconversionafterthecurrentconversionis complete.WhenthecurrentA/Dconversioniscomplete,theconverteddigitaldatawillbestoredinthe A/DdataregisterpairandthenlatchedafterhalfanA/Dclockcycle.IftheSTARTbitissetto1inhalf anA/DclockcycleaftertheendofA/Dconversion,theconverteddigitaldatastoredintheA/Ddata registerpairwillbechanged.Therefore,itisrecommendedtoinitiatethenextA/Dconversionaftera certainperiodgreaterthanhalfanA/DclockcycleattheendofcurrentA/Dconversion. ENADC START ADBZ SACS[�:0] off on off on tON�ST tADS A/D sa�pling ti�e tADS A/D sa�pling ti�e Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion Sta�t of A/D �onve�sion End of A/D �onve�sion End of A/D �onve�sion tADC A/D �onve�sion ti�e tADC A/D �onve�sion ti�e tADC A/D �onve�sion ti�e 0011B 0010B 0000B 0001B A/D �hannel swit�h A/D Conversion Timing |
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