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HT45F65 Datasheet(PDF) 201 Page - Holtek Semiconductor Inc |
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HT45F65 Datasheet(HTML) 201 Page - Holtek Semiconductor Inc |
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201 / 231 page  Rev. 1.60 �00 �ove��e� ��� �01� Rev. 1.60 �01 �ove��e� ��� �01� HT45F65/HT45F66/HT45F67 Glucose Meter 8-Bit Flash MCU UART Interrupt Structure SeveralindividualUARTconditionscangenerateaUARTinterrupt.Whentheseconditionsexist, alowpulsewillbegeneratedtogettheattentionofthemicrocontroller.Theseconditionsarea transmitterdataregisterempty,transmitteridle,receiverdataavailable,receiveroverrun,address detectandanRXpinwake-up.Whenanyoftheseconditionsarecreated,ifitscorresponding interruptcontrolisenabledandthestackisnotfull,theprogramwilljumptoitscorresponding interruptvectorwhereitcanbeservicedbeforereturningtothemainprogram.Fourofthese conditionshavethecorrespondingUSRregisterflagswhichwillgenerateaUARTinterruptifits associatedinterruptenablecontrolbitintheUCR2registerisset.Thetwotransmitterinterrupt conditionshavetheirowncorrespondingenablecontrolbits,whilethetworeceiverinterrupt conditionshaveasharedenablecontrolbit.Theseenablebitscanbeusedtomaskoutindividual UARTinterruptsources. Theaddressdetectcondition,whichisalsoaUARTinterruptsource,doesnothaveanassociated flag,butwillgenerateaUARTinterruptwhenanaddressdetectconditionoccursifitsfunction isenabledbysettingtheADDENbitintheUCR2register.AnRXpinwake-up,whichisalsoa UARTinterruptsource,doesnothaveanassociatedflag,butwillgenerateaUARTinterruptif themicrocontrolleriswokenupbyafallingedgeontheRXpin,iftheWAKEandRIEbitsinthe UCR2registerareset.NotethatintheeventofanRXwake-upinterruptoccurring,therewillbea certainperiodofdelay,commonlyknownastheSystemStart-upTime,fortheoscillatortorestart andstabilizebeforethesystemresumesnormaloperation. NotethattheUSRregisterflagsarereadonlyandcannotbeclearedorsetbytheapplication program,neitherwilltheybeclearedwhentheprogramjumpstothecorrespondinginterrupt servicingroutine,asisthecaseforsomeoftheotherinterrupts.Theflagswillbecleared automaticallywhencertainactionsaretakenbytheUART,thedetailsofwhicharegiveninthe UARTregistersection.TheoverallUARTinterruptcanbedisabledorenabledbytherelated interruptenablecontrolbitsintheinterruptcontrolregistersofthemicrocontrollertodecidewhether theinterruptrequestedbytheUARTmoduleismaskedoutorallowed. US R Re gi st er Tr ans mi tte r Em pt y Fl ag T XI F Tr ans mi tt er Id le Fl ag T ID LE Re ce iv er D at a Av ai la bl e RX IF Re ce iv er O ve rr un Fl ag O ER R RX 7 if B NO =0 RX 8 if B NO =1 AD DE N 0 1 0 1 RX P in Wa ke -u p WA KE 0 1 UCR2 R egi st er TE IE TI IE RI E UA RT I nt er r upt R eques t Fl ag UR F UCR 2 R egi st er 0 1 0 1 0 1 OR To M CU I nt er r upt C on tr ol le r UART Interrupt Scheme |
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