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WM8950 Datasheet(PDF) 9 Page - Cirrus Logic

Part # WM8950
Description  ADC with Microphone Input and Programmable Digital Filters
PDF  60 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8950 Datasheet(HTML) 9 Page - Cirrus Logic

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WM8950
Rev 4.5
9
AUDIO INTERFACE TIMING
– SLAVE MODE
BCLK
FRAME
t
BCH
t
BCL
t
BCY
ADCDAT
t
LRSU
t
LRH
t
DD
Figure 3 Digital Audio Data Timing
– Slave Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25
oC, Slave Mode, fs=48kHz, MCLK= 256fs,
24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
FRAME set-up time to BCLK rising edge
tLRSU
10
ns
FRAME hold time from BCLK rising edge
tLRH
10
ns
ADCDAT propagation delay from BCLK falling edge
tDD
20
ns
Note: BCLK period should always be greater than or equal to MCLK period.



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