WM8950 datasheet(44/60 Pages) CIRRUS

44 / 60 page

WM8950

Rev 4.5

GENERAL PURPOSE INPUT/OUTPUT

The CSB/GPIO pin can be configured to perform a variety of useful tasks by setting the GPIOSEL

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

GPIO

control

2:0

GPIOSEL

000

CSB/GPIO pin function select:

000=CSB input

001=Reserved

010=Temp ok

011=Automute active

100=PLL clk o/p

101=PLL lock

110=Reserved

111=Reserved

GPIOPOL

GPIO Polarity invert

0=Non inverted

1=Inverted

5:4

OPCLKDIV

PLL Output clock division ratio

00=divide by 1

01=divide by 2

10=divide by 3

11=divide by 4

Table 39 CSB/GPIO Control

CONTROL INTERFACE

SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS

The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin

determines the 2 or 3 wire mode as shown in Table 40.

The WM8950 is controlled by writing to registers through a serial control interface. A control word

consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is

accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each

control register.

MODE

INTERFACE FORMAT

Low

2 wire

High

3 wire

Table 40 Control Interface Mode Selection

3-WIRE SERIAL CONTROL MODE

In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on

CSB/GPIO latches in a complete control word consisting of the last 16 bits.

B15

B14

B13

B12

B11

B10

SDIN

SCLK

CSB

control register address

control register data bits

latch

Figure 27 3-Wire Serial Control Interface

WM8950 Datasheet(PDF) 44 Page - Cirrus Logic

WM8950 Datasheet(HTML) 44 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL