WM8950 datasheet(36/60 Pages) CIRRUS

36 / 60 page

WM8950

Rev 4.5

DIGITAL AUDIO INTERFACES

The audio interface has three pins:



ADCDAT: ADC data output



FRAME: Data alignment clock



BCLK: Bit clock, for synchronisation

The clock signals BCLK, and FRAME can be outputs when the WM8950 operates as a master, or

inputs when it is a slave (see Master and Slave Mode Operation, below).

Five different audio data formats are supported:



Left justified



Right justified



I2S



DSP mode

All of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

MASTER AND SLAVE MODE OPERATION

The WM8950 audio interface may be configured as either master or slave. As a master interface

device the WM8950 generates BCLK and FRAME and thus controls sequencing of the data transfer

on ADCDAT. To set the device to master mode register bit MS should be set high. In slave mode

(MS=0), the WM8950 responds with data to clocks it receives over the digital audio interfaces.

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following an FRAME

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each FRAME transition.

LEFT

PHASE

RIGHT

PHASE

FRAME

BCLK

ADCDAT

1/fs

n-2 n-1

LSB

MSB

Figure 19 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a FRAME

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each FRAME transition.

WM8950 Datasheet(PDF) 36 Page - Cirrus Logic

WM8950 Datasheet(HTML) 36 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL