M0518 datasheet(39/72 Pages) ETC2

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NuMicro M0518 Series Datasheet

Feb 08, 2017

Page 39 of 72

Revision 1.01

6.3.4 Frequency Divider Output

This device is equipped with a power-of-2 frequency divider which is composed by16 chained

divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one

multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided

clocks with the frequency from Fin/2

1 to F

in/2

16 where Fin is input clock frequency to the clock

divider.

The output formula is Fout = Fin/2

(N+1), where F

in is the input clock frequency, Fout is the clock

divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).

When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0

to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low

state and stay in low state.

If DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass

power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly.

HCLK

Reserved

4~24 MHz

22.1184 MHz

FRQDIV_S (CLKSEL2[3:2])

FDIV_EN (APBCLK[6])

FRQDIV_CLK

Figure 6-7 Clock Source of Frequency Divider

0000

0001

1110

1111

16 to 1

MUX

1/2

1/22

1/23

1/215

1/216

…...

FSEL

(FRQDIV[3:0])

CLKO

FRQDIV_CLK

16 chained

divide-by-2 counter

DIVIDER_EN

(FRQDIV[4])

Enable

divide-by-2 counter

DIVIDER1

(FRQDIV[5])

Figure 6-8 Frequency Divider Block Diagram

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