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S1313 Datasheet(PDF) 19 Page - Seiko Instruments Inc |
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S1313 Datasheet(HTML) 19 Page - Seiko Instruments Inc |
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19 / 56 page ![]() SUPER LOW CURRENT CONSUMPTION LOW DROPOUT CMOS VOLTAGE REGULATOR Rev.2.1_00 S-1313 Series 19 Operation 1. Basic operation Figure 17 shows the block diagram of the S-1313 Series. The error amplifier compares the reference voltage (Vref) with feedback voltage (Vfb), which is the output voltage resistance-divided by feedback resistors (Rs and Rf). It supplies the gate voltage necessary to maintain the constant output voltage which is not influenced by the input voltage and temperature change, to the output transistor. *1 *1. Parasitic diode VSS Current supply − + Vfb Vref VIN VOUT Rf Rs Error amplifier Reference voltage circuit Figure 17 2. Output transistor In the S-1313 Series, a low on-resistance P-channel MOS FET is used as the output transistor. Be sure that VOUT does not exceed VIN + 0.3 V to prevent the voltage regulator from being damaged due to reverse current flowing from the VOUT pin through a parasitic diode to the VIN pin, when the potential of VOUT became higher than VIN. |
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