LAN91C100FD datasheet(22/79 Pages) SMSC

22 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 22

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

The default bit values upon hard reset are highlighted below each register.

Table 5.1 - Internal I/O Space Mapping

BANK0

BANK1

BANK2

BANK3

TCR

CONFIG

MMU COMMAND

MT0-1

EPH STATUS

BASE

PNR

ARR

MT2-3

RCR

IA0-1

FIFO PORTS

MT4-5

COUNTER

IA2-3

POINTER

MT6-7

MIR

IA4-5

DATA

MGMT

MCR

GENERAL PURPOSE

DATA

REVISION

RESERVED (0)

CONTROL

INTERRUPT

ERCV

BANK SELECT

A special BANK (BANK7) exists to support the addition of external registers.

BANK SELECT REGISTER

OFFSET

NAME

TYPE

SYMBOL

BANK SELECT

READ/WRITE

BSR

HIGH

BYTE

LOW

BYTE

BS2

BS1

BS0

BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to

select the register bank in use.

The upper byte always reads as 33h and can be used to help determine the I/O location of the

LAN91C100FD.

The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2.

Note:

The bank select register can be accessed as a doubleword at offset Ch, as a word at offset Eh, or

as at offset Fh, however a doubleword write to offset Ch will write the BANK SELECT REGISTER

but will not write the registers Ch and Dh.

BANK 7 has no internal registers other than the BANK SELECT REGISTER itself. On valid cycles where

BANK7 is selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of

external registers.

Note:

BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be

done if the Revision Control register indicates the device is the LAN91C100FD.

LAN91C100FD Datasheet(PDF) 22 Page - SMSC Corporation

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