LAN91C100FD datasheet(57/79 Pages) SMSC

57 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

SMSC DS – LAN91C100FD Rev. D

Page 57

Rev. 10/14/2002

PRELIMINARY

VL BUS

SIGNAL

LAN91C100

SIGNAL

NOTES

nBE0 nBE1

nBE2 nBE3

nBE0 nBE1

nBE2 nBE3

Byte enables. Latched transparently by nADS rising edge.

nADS

nADS, nCYCLE

Address Strobe is connected directly to the VL bus. nCYCLE is

created typically by using nADS delayed by one LCLK.

IRQn

INTR0-INTR3

Typically uses the interrupt lines on the ISA edge connector of

VL bus

D0-D31

32 bit data bus. The bus byte(s) used to access the device are a

function of nBE0-nBE3:

nBE0

nBE1

nBE2

nBE3

Double word access

Low word access

High word access

Byte 0 access

Byte 1 access

Byte 2 access

Byte 3 access

Not used = tri-state on reads, ignored on writes. Note that nBE2

and nBE3 override the value of A1, which is tied low in this

application.

nLDEV

nLDEV is a totem pole output. nLDEV is active on valid decodes

of A15-A4 and AEN=0.

UNUSED PINS

VCC

nRD nWR

GND

A1 nVLBUS

OPEN

nDATACS

LAN91C100FD Datasheet(PDF) 57 Page - SMSC Corporation

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