LAN91C100FD datasheet(28/79 Pages) SMSC

28 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 28

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

NO WAIT - When set, does not request additional wait states. An exception to this are accesses to the

Data Register if not ready for a transfer. When clear, negates IOCHRDY for two to three clocks on any

cycle to the LAN91C100FD.

FULL STEP - This bit is a general purpose output port. Its inverse value drives pin nFSTEP and it is

typically connected to SEL pin of the LAN83C694. It can be used to select the signaling mode for the AUI

or as a general purpose non-volatile configuration pin. Defaults low.

AUI SELECT - This bit is a general purpose output port. Its value drives pin AUISEL and it is typically

connected to MODE1 pin of the LAN83C694. It can be used to select AUI vs. 10BASE-T, or as a general

purpose non-volatile configuration pin. Defaults low.

Reserved - Must be 0.

INT SEL1-0 - Used to select one out of four interrupt pins. The three unused interrupts are tristated.

INT SEL1

INT SEL0

INTERRUPT PIN

USED

INTR0

INTR1

INTR2

INTR3

BANK 1

OFFSET

NAME

TYPE

SYMBOL

BASE ADDRESS REGISTER

READ/WRITE

BAR

This register holds the I/O address decode option chosen for the LAN91C100FD. It is part of the EEPROM

saved setup and is not usually modified during run-time.

HIGH

BYTE

A15

A14

A13

LOW

BYTE

Reserved

A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the

IOBASE for the LAN91C100FD‘s registers. The 64k I/O space is fully decoded by the LAN91C100FD

down to a 16 location space, therefore the unspecified address lines A4, A10, A11 and A12 must be all

zeros.

All bits in this register are loaded from the serial EEPROM.

The I/O base decode defaults to 300h

(namely, the high byte defaults to 18h).

Reserved - Must be 0.

BANK 1

OFFSET

NAME

TYPE

SYMBOL

4 THROUGH 9

INDIVIDUAL ADDRESS

REGISTERS

READ/WRITE

IAR

These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or

EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not

modify the EEPROM Individual Address contents. Bit 0 of Individual Address 0 register corresponds to the

first bit of the address on the cable.

LAN91C100FD Datasheet(PDF) 28 Page - SMSC Corporation

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