LAN91C100FD datasheet(50/79 Pages) SMSC

50 / 79 page

FEAST Fast Ethernet Controller with Full Duplex Capability

Rev. 10/14/2002

Page 50

SMSC DS – LAN91C100FD Rev. D

PRELIMINARY

Memory is always requested by the side that needs to write into it, that is: the CPU for transmit or the MAC

for receive. The CPU can control the number of bytes it requests for transmit but it cannot determine the

number of bytes the receive process is going to demand. Furthermore, the receive process requests will

be dependent on network traffic, in particular on the arrival of broadcast and multicast packets that might

not be for the node, and that are not subject to upper layer software flow control.

In order to prevent unwanted traffic from using too much memory, the CPU can program a "memory

reserved for transmit" parameter. If the free memory falls below the "memory reserved for transmit" value,

MMU requests from the MAC block will fail and the packets will overrun and be ignored. Whenever

enough memory is released, packets can be received again. If the reserved value is too large, the node

might lose data which is an abnormal condition. If the value is kept at zero, memory allocation is handled

on first-come first-served basis for the entire memory capacity.

Note that with the memory management built into the LAN91C100FD, the CPU can dynamically program

this parameter. For instance, when the driver does not need to enqueue transmissions, it can allow more

memory to be allocated for receive (by reducing the value of the reserved memory). Whenever the driver

needs to burst transmissions it can reduce the receive memory allocation. The driver program the

parameter as a function of the following variables:

Free memory (read only register)

Memory size (read only register)

The reserved memory value can be changed on the fly. If the MEMORY RESERVED FOR TX value is

increased above the FREE MEMORY, receive packets in progress are still received, but no new packets

are accepted until the FREE MEMORY increases above the MEMORY RESERVED value.

5.6

Interrupt Generation

The interrupt strategy for the transmit and receive processes is such that it does not represent the

bottleneck in the transmit and receive queue management between the software driver and the controller.

For that purpose there is no register reading necessary before the next element in the queue (namely

transmit or receive packet) can be handled by the controller. The transmit and receive results are placed

in memory.

The receive interrupt will be generated when the receive queue (FIFO of packets) is not empty and receive

interrupts are enabled. This allows the interrupt service routine to process many receive packets without

exiting, or one at a time if the ISR just returns after processing and removing one.

There are two types of transmit interrupt strategies:

One interrupt per packet.

One interrupt per sequence of packets.

The strategy is determined by how the transmit interrupt bits and the AUTO RELEASE bit are used.

TX INT bit - Set whenever the TX completion FIFO is not empty.

TX EMPTY INT bit - Set whenever the TX FIFO is empty.

AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and their

memory is released automatically.

One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the

completion result in memory and process the interrupt one packet at a time. Depending on the

completion code the driver will take different actions. Note that the transmit process is working in

parallel and other transmissions might be taking place. The LAN91C100FD is virtually queuing the

packet numbers and their status words.

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