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AD4000 Datasheet(PDF) 32 Page - Analog Devices

Part # AD4000
Description  Precision, Pseudo Differential, SAR ADCs
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD4000 Datasheet(HTML) 32 Page - Analog Devices

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AD4000/AD4004/AD4008
Data Sheet
Rev. C | Page 32 of 36
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is typically used when multiple AD4000/AD4004/
AD4008 devices are connected to an SPI-compatible digital host.
A connection diagram example using two AD4000/AD4004/
AD4008 devices is shown in Figure 58, and the corresponding
timing diagram is shown in Figure 59.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. If SDI and CNV are low, SDO is
driven low. Prior to the minimum conversion time, SDI can
select other SPI devices, such as analog multiplexers; however,
SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator.
When the conversion is complete, the AD4000/AD4004/
AD4008 enter the acquisition phase and power down. Each
ADC result can be read by bringing its SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided it has an acceptable hold time. After the
16th SCK falling edge or when SDI goes high (whichever occurs
first), SDO returns to high impedance and another AD4000/
AD4004/AD4008 can be read.
AD4000/
AD4004/
AD4008
SDI
SDO
CNV
SCK
DEVICE A
CONVERT
DATA IN
CLK
DIGITAL HOST
AD4000/
AD4004/
AD4008
SDI
SDO
CNV
SCK
DEVICE B
CS1
CS2
Figure 58. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
SDO
D15
D14
D13
D1
D0
tDIS
SCK
1
2
3
30
31
32
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI(CS1)
CNV
tSSDICNV
tHSDICNV
D1
14
15
tSCK
tSCKL
tSCKH
D0
D15
D14
17
18
16
SDI(CS2)
tQUIET2
Figure 59. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing Diagram



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