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AD4003/AD4007/AD4011

Data Sheet

Rev. B | Page 18 of 38

CONVERTER OPERATION

The AD4003/AD4007/AD4011 are SAR-based ADCs using a

charge redistribution sampling digital-to-analog converter

(DAC). Figure 31 shows the simplified schematic of the ADC.

The capacitive DAC consists of two identical arrays of 18 binary

weighted capacitors, which are connected to the comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to GND via the SW+ and

SW− switches. All independent switches connect the other

terminal of each capacitor to the analog inputs. Therefore, the

capacitor arrays are used as sampling capacitors and acquire the

analog signal on the IN+ and IN− inputs.

When the acquisition phase is complete and the CNV input

goes high, a conversion phase initiates. When the conversion

phase begins, SW+ and SW− are opened first. The two capacitor

arrays are then disconnected from the inputs and connected to

the GND input. The differential voltage between the IN+ and

IN− inputs captured at the end of the acquisition phase is applied

to the comparator inputs, causing the comparator to become

unbalanced. By switching each element of the capacitor array

between GND and VREF, the comparator input varies by binary

weighted voltage steps (VREF/2, VREF/4, …, VREF/262,144). The

control logic toggles these switches, starting with the MSB, to

bring the comparator back into a balanced condition. After the

completion of this process, the control logic generates the ADC

output code and a busy signal indicator.

Because the AD4003, AD4007, and AD4011 have on-board

conversion clocks, the serial clock (SCK) is not required for the

conversion process.

TRANSFER FUNCTIONS

The ideal transfer characteristics for the AD4003/AD4007/

AD4011 are shown in Figure 32 and Table 9.

100...000

100...001

100...010

011...101

011...110

011...111

ANALOG INPUT

+FSR – 1.5 LSB

+FSR – 1 LSB

–FSR + 1 LSB

–FSR

–FSR + 0.5 LSB

Figure 32. ADC Ideal Transfer Function (FSR Is Full-Scale Range)

Table 9. Output Codes and Ideal Input Voltages

Description

Analog Input, VREF = 5 V

VREF = 5 V with Span Compression Enabled

Digital Output Code (Hex)

FSR − 1 LSB

+4.999962 V

+3.999969 V

0x1FFFF1

Midscale + 1 LSB

+38.15 μV

+30.5 μV

0x00001

Midscale

0 V

0x00000

Midscale − 1 LSB

−38.15 μV

−30.5 μV

0x3FFFF

−FSR + 1 LSB

−4.999962 V

−3.999969 V

0x20001

−FSR

−5 V

−4 V

0x200002

1 This output code is also the code for an overranged analog input (VIN+ − VIN− above VREF with the span compression disabled and above 0.8 ×VREF with the span

compression enabled).

2 This output code is also the code for an underranged analog input (VIN+ − VIN− below −VREF with the span compression disabled and above 0.8 ×VREF with the span

compression enabled).

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