AD4003/AD4007/AD4011

Data Sheet

Rev. B | Page 20 of 38

10µF

REF

VDD

VIO

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4003/AD4007/

AD4011

3-WIRE/4-WIRE

INTERFACE

1.8V

1.8V TO 5V

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

4.096V

0.1µF

R3

1kΩ

+IN

V+

–IN

–OUT

+OUT

R4

1kΩ

10kΩ

10kΩ

R2

1kΩ

R

R

DIFFERENTIAL

AMPLIFIER

R1

1kΩ

0.1µF

HOST

SUPPLY

V–

C

C

REF

V+ = 5V

LDO

AMP

0

0

0.1µF

Figure 35. Typical Application Diagram with a Fully Differential Amplifier

REF

VDD

VIO

GND

IN+

IN–

SDI

SCK

SDO

CNV

AD4003/AD4007/

AD4011

1.8V TO 5V

+IN

–IN

R4

1kΩ

DIFFERENTIAL

AMPLIFIER

R1

1kΩ

V–

AMP

0V

1.8V

10µF

R3

1kΩ

V+

–OUT

+OUT

R2

1kΩ

R

R

0.1µF

VREF/2

HOST

SUPPLY

C

C

REF

V+ = 5V

LDO

10kΩ

10kΩ

4.096V

0.1µF

0.1µF

3-WIRE/4-WIRE

INTERFACE

DIGITAL HOST

(MICROPROCESSOR/

FPGA)

Figure 36. Typical Application Diagram for Single-Ended to Differential Conversion with a Fully Differential Amplifier

ANALOG INPUTS

Figure 37 shows an equivalent circuit of the analog input

structure, including the overvoltage clamp of the AD4003/

AD4007/AD4011.

REF

D1

IN+/IN–

GND

CLAMP

0V TO 15V

D2

Figure 37. Equivalent Analog Input Circuit

Input Overvoltage Clamp Circuit

Most ADC analog inputs, IN+ and IN−, have no overvoltage

protection circuitry apart from ESD protection diodes. During

an overvoltage event, an ESD protection diode from an analog

input pin (IN+ or IN−) pin to REF forward biases and shorts

the input pin to REF, potentially overloading the reference or

causing damage to the device. The AD4003/AD4007/AD4011

internal overvoltage clamp circuit with a larger external resistor

diodes and protects the ADC inputs against dc overvoltages.