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MT9V403 Datasheet(PDF) 16 Page - Micron Technology |
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MT9V403 Datasheet(HTML) 16 Page - Micron Technology |
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16 / 33 page ![]() 1/2-INCH VGA (WITH FREEZE-FRAME) CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR 09005aef80c07280 Micron Technology, Inc., reserves the right to change products or specifications without notice. MT9V403_DS.fm - Rev. B 1/04 EN 16 ©2004 Micron Technology. Inc. W/R Reg17 VLN2 bias control. Bit 7 = 1 disable internal bias. Bit 0 = 1 high bias. Bit 1 = 1 low bias. Bits 3–15 not used, set to 0. 0000000000000000 00010001 W/R Reg18 VLN_OUT bias control. Bit 7 = 1disable internal bias. Bit 0 = 1 high bias. Bit 1 = 1 low bias. Bits 3–6, 8–15 not used, set to 0. 0000000000000000 00010010 W/R Reg19 VLN1 bias control. Bit 7 = disable internal bias. Bit 0 = 1 high bias. Bit 1 = 1 low bias. Bits 3–6, 8–15 not used, set to 0. 0000000000000000 00010011 W/R Reg20 VLP bias control. Bit 7 = 1 disable internal control. Bit 0 = 1 high bias. Bit 1 = 1 low bias. Bits 3–6, 8–15 not used, set to 0. 0000000000000000 00010100 W/R Reg21 VREF bias control. Bit 0-3 = bias value. Bit 7 = 1 disable internal bias. Bits 4–6, 8–15 not used, set to 0. 0000000000001010 00010101 W/R Reg22 VREF2 bias control. Bit 0-3 bias value. Bit 7= 1 disable internal bias. Bits 4–6, 8–15 not used, set to 0. 0000000000001010 00010110 W/R Reg23 VOFF bias control. Bit 0-3 bias value. Bit 6 = 1 sign of offset is negative. Bit 7 = 1 disable internal bias. Bits 4–5, 8–15 not used, set to 0. 0000000000000000 00010111 W/R Reg29 VLN2 bias booster. Bit 3 = 1 high bias. 0000000000000000 00011101 W/R Reg43 Blue gain settings. Default gain is 2. Gain settings range is from 1 (00000001) to 18 (00010010). ********00000010 00101011 W/R Reg44 Green 1 gain settings. Default gain is 2. Gain settings range is from 1 (00000001) to 18 (00010010). ********00000010 00101100 W/R Reg45 Green 2 gain settings. Default gain is 2. Gain settings range is from 1 (00000001) to 18 (00010010). ********00000010 00101101 W/R Reg46 Red gain settings. Default gain is 2. Gain settings range is from 1 (00000001) to 18 (00010010). ********00000010 00101110 W/R Reg53 Global gain control. Bit 0 = 1 gain is multiplied by factor of 0.5 *********0000000 00110101 Table 4: Complete Register Description (continued) READ/ WRITE CONTROL REGISTER NAME FUNCTION DEFAULT CONTENTS REGISTER ADDRESS |
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