1/2-INCH VGA (WITH FREEZE-FRAME) CMOS

ACTIVE-PIXEL DIGITAL IMAGE SENSOR

09005aef80c07280

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT9V403_DS.fm - Rev. B 1/04 EN

24

©2004 Micron Technology. Inc.

Figure 29: Board Connections

NOTE:

1. VLN1, VLP, VOFF, VREF, VREF1, VLN2, and VREF2 are generated on-chip, but user may disable internal bias (via two-

wire serial interface) and apply external voltages to sensor. VREF1DRV is generated on chip but its internal bias can-

not be disabled. VRST_PIX and VRSTLOW are not generated internally and external voltages must be applied.

2. All bias pins should be decoupled with 0.1µF ceramic and 10µF electrolytic capacitors. (Please see board connections.)

Capacitors should be placed as physically close as possible to the MT9V403 package.

3. Digital outputs can drive standard CMOS circuits with 30pF load, but less load capacitance results in less substrate

noise on-chip. This is recommended to minimize load capacitance for better noise performance.

DATA0 3

DATA1 2

DATA2 1

DATA3 48

DATA4 47

DATA5 46

DATA6 42

DATA7 45

DATA8 40

DATA9 41

Pixel

Data

Output

8

VREF1DRV

17

VLN1

19

VLP

9

VREF1

7

VREF2

14

VTEST1

Analog +3.3V

Digital +3.3V

1.5k

Ω

1k

Ω

0.1µF

10µF

0.1µF

10µF

Analog +3.3V

0.1µF

10µF

Analog +3.3V

1k

Ω

1k

Ω

0.1µF

10µF

Analog +3.3V

1k

Ω

0.1µF

10µF

Analog +3.3V

1k

Ω

0.1µF

10µF

Analog +3.3V

1k

Ω

0.1µF

10µF

Analog +3.3V

1k

Ω

0.1µF

10µF

Analog +3.3V

1k

Ω

0.1µF

10µF

Analog +3.3V

1k

Ω

0.1µF

10µF

Analog +3.3V

1k

Ω

0.1µF

10µF

Analog Ground

Digital Ground

Controller

Interface

39

SDATA

32

FRAME_SYNC_N

37

SYSCLK

29

EXPOSE

31

ROW_VALID/LD_SHFT_N

38

SCLK

30

FRAME_VALID/ROW_STRT

33

LRST_N

26

PG_N

25

TX

24

RESMEM

VRSTLOW

23

VLNS

18

VLN2

21

VRST_PIX

20

VREF

16

VOFF

13