AD7175-2 datasheet(23/63 Pages) AD

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AD7175-2

Data Sheet

Rev. B | Page 22 of 62

Reading the ID register is the recommended method for verifying

correct communication with the device. The ID register is a

read only register and contains the value 0x0CDX for the

AD7175-2. The communications register and the ID register

details are described in Table 8 and Table 9.

AD7175-2 RESET

In situations where interface synchronization is lost, a write

operation of at least 64 serial clock cycles with DIN high returns the

ADC to the default state by resetting the entire device, including

the register contents. Alternatively, if CS is being used with the

digital interface, returning CS high sets the digital interface to

the default state and halts any serial interface operation.

CONFIGURATION OVERVIEW

After power-on or reset, the AD7175-2 default configuration is

as follows:

Channel configuration. CH0 is enabled, AIN0 is selected

as the positive input, and AIN1 is selected as the negative

input. Setup 0 is selected.

Setup configuration. The internal reference and the analog

input buffers are enabled. The reference input buffers are

disabled.

Filter configuration. The sinc5 + sinc 1 filter is selected and

the maximum output data rate of 250 kSPS is selected.

ADC mode. Continuous conversion mode and the internal

oscillator are enabled.

Interface mode. CRC and data + status output are disabled.

Note that only a few of the register setting options are shown;

this list is just an example. For full register information, see the

Figure 48 shows an overview of the suggested flow for changing

the ADC configuration, divided into the following three blocks:

Channel configuration (see Box A in Figure 48)

Setup configuration (see Box B in Figure 48)

ADC mode and interface mode configuration (see Box C

in Figure 48)

Channel Configuration

The AD7175-2 has four independent channels and four independ-

ent setups. The user can select any of the analog input pairs on

any channel, as well as any of the four setups for any channel,

giving the user full flexibility in the channel configuration. This

also allows per channel configuration when using differential

inputs and single-ended inputs because each channel can have a

dedicated setup.

Channel Registers

The channel registers select which of the five analog input pins

(AIN0 to AIN4) are used as either the positive analog input (AIN+)

or the negative analog input (AIN−) for that channel. This register

also contains a channel enable/disable bit and the setup selection

bits, which pick which of the four available setups to use for this

channel.

When the AD7175-2 is operating with more than one channel

enabled, the channel sequencer cycles through the enabled

channels in sequential order, from Channel 0 to Channel 3. If a

channel is disabled, it is skipped by the sequencer. Details of the

channel register for Channel 0 are shown in Table 10.

ADC MODE AND INTERFACE MODE CONFIGURATION

SELECT ADC OPERATING MODE, CLOCK SOURCE,

ENABLE CRC, DATA + STATUS, AND MORE

SETUP CONFIGURATION

4 POSSIBLE ADC SETUPS

SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE

CHANNEL CONFIGURATION

SELECT POSITIVE AND NEGATIVE INPUT FOR EACH ADC CHANNEL

SELECT ONE OF 4 SETUPS FOR ADC CHANNEL

Figure 48. Suggested ADC Configuration Flow

Table 8. Communications Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x00

COMMS

[7:0]

WEN

R/W

0x00

Table 9. ID Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x07

[15:8]

ID[15:8]

0x0CDX

[7:0]

ID[7:0]

AD7175-2 Datasheet(PDF) 23 Page - Analog Devices

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