AD7175-2 datasheet(32/63 Pages) AD

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Data Sheet

AD7175-2

Rev. B | Page 31 of 62

DIGITAL FILTERS

The AD7175-2 has three flexible filter options to allow

optimization of noise, settling time, and rejection:

Sinc5 + sinc1 filter

Sinc3 filter

Enhanced 50 Hz and 60 Hz rejection filters

SINC1

SINC5

SINC3

50Hz AND 60Hz

POSTFILTER

Figure 57. Digital Filter Block Diagram

The filter and output data rate are configured by setting the

appropriate bits in the filter configuration register for the

selected setup. Each channel can use a different setup and

therefore, a different filter and output data rate. See the Register

Details section for more information.

SINC5 + SINC1 FILTER

The sinc5 + sinc1 filter is targeted at multiplexed applications and

achieves single cycle settling at output data rates of 10 kSPS and

lower. The sinc5 block output is fixed at the maximum rate of

250 kSPS, and the sinc1 block output data rate can be varied to

control the final ADC output data rate. Figure 58 shows the

frequency domain response of the sinc5 + sinc1 filter at a 50 SPS

output data rate. The sinc5 + sinc1 filter has a slow roll-off over

frequency and narrow notches.

–120

150

100

FREQUENCY (Hz)

–100

–80

–60

–40

–20

Figure 58. Sinc5 + Sinc1 Filter Response at 50 SPS ODR

The output data rates with the accompanying settling time and

rms noise for the sinc5 + sinc1 filter are shown in Table 19 and

Table 20.

SINC3 FILTER

The sinc3 filter achieves the best single-channel noise performance

at lower rates and is, therefore, most suitable for single-channel

applications. The sinc3 filter always has a settling time equal to

tSETTLE = 3/Output Data Rate

Figure 59 shows the frequency domain filter response for the

sinc3 filter. The sinc3 filter has good roll-off over frequency and

has wide notches for good notch frequency rejection.

–120

150

100

FREQUENCY (Hz)

–100

–80

–60

–40

–20

–110

–90

–70

–50

–30

–10

Figure 59. Sinc3 Filter Response

The output data rates with the accompanying settling time and

rms noise for the sinc3 filter are shown in Table 21 and Table 22. It

is possible to finely tune the output data rate for the sinc3 filter by

setting the SINC3_MAPx bit in the filter configuration registers.

If this bit is set, the mapping of the filter register changes to directly

program the decimation rate of the sinc3 filter. All other options

are eliminated. The data rate when on a single channel can be

calculated using the following equation:

4:0]

FILTCONx[1

Rate

Data

Output

MOD

where:

fMOD is the modulator rate (MCLK/2) and is 8 MHz for a

16 MHz MCLK.

FILTCONx[14:0] are the contents on the filter configuration

registers excluding the MSB.

For example, an output data rate of 50 SPS can be achieved with

SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a

value of 5000.

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