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AD7175-2 Datasheet(PDF) 28 Page - Analog Devices |
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AD7175-2 Datasheet(HTML) 28 Page - Analog Devices |
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28 / 63 page ![]() Data Sheet AD7175-2 Rev. B | Page 27 of 62 Figure 52 shows an example of how the channel registers span between the analog input pins and the setup configurations downstream. In this example, one differential input and two single- ended inputs are required. The single-ended inputs are the AIN2/ AIN4 and AIN3/AIN4 combinations. The differential input pairs is AIN0/AIN1and uses Setup 0. The two single-ended input pairs are set up as diagnostics; therefore, use a separate setup from the differential input but share a setup between them, Setup 1. Given that two setups are selected for use, the SETUPCON0 and SETUPCON1 registers are programmed as required, and the FILTCON0 and FILTCON1 registers are also programmed as desired. Optional gain and offset correction can be employed on a per setup basis by programming the GAIN0 and GAIN1 registers and the OFFSET0 and OFFSET1 registers. In the example shown in Figure 52, the CH0 to CH2 registers are used. Setting the MSB in each of these registers, the CH_EN0 to CH_EN2 bits enable the three combinations via the crosspoint mux. When the AD7175-2 converts, the sequencer transitions in ascending sequential order from CH0 to CH1 to CH2 before looping back to CH0 to repeat the sequence. SETUP CONFIG REGISTERS FILTER CONFIG REGISTERS OFFSET REGISTERS GAIN REGISTERS* SELECT PERIPHERAL FUNCTIONS FOR ADC CHANNEL SELECT ANALOG INPUT PARTS ENABLE THE CHANNEL SELECT SETUP SELECT DIGITAL FILTER TYPE AND OUTPUT DATA RATE GAIN CORRECTION OPTIONALLY PROGRAMMED PER SETUP AS REQUIRED (*FACTORY CALIBRATED) OFFSET CORRECTION OPTIONALLY PROGRAMMED PER SETUP AS REQUIRED 0x20 0x21 0x22 0x23 0x28 0x29 0x2A 0x2B 0x38 0x39 0x3A 0x3B 0x30 0x31 0x32 0x33 SETUPCON3 SETUPCON0 SETUPCON2 SETUPCON1 FILTCON3 FILTCON0 FILTCON2 FILTCON1 GAIN3 GAIN0 GAIN2 GAIN1 OFFSET3 OFFSET0 OFFSET2 OFFSET1 0x10 CH0 0x11 CH1 0x12 CH2 0x13 CH3 AIN0 AIN1 AIN2 AIN3 AIN4 CHANNEL REGISTERS DATA OUTPUT CODING REFERENCE SOURCE INPUT BUFFERS SINC5 + SINC1 SINC3 SINC3 MAP ENHANCED 50Hz AND 60Hz Figure 52. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups |
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