AD9683 datasheet(27/45 Pages) AD

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AD9683

Data Sheet

Rev. D | Page 26 of 44

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There are three identification values: device identification

(DID), bank identification (BID), and lane identification

(LID). DID and BID are device specific; therefore, they can

be used for link identification.

Set the number of frames per multiframe, K.

•

Per the JESD204B specification, a multiframe is defined as a

group of K successive frames, where K is between 1 and 32,

and it requires that the number of octets be between 17 and

1024. The K value is set to 32 by default in Address 0x70,

Bits[7:0]. Note that the K value is the register value plus 1.

•

The K value can be changed; however, it must comply with

a few conditions. The AD9683 uses a fixed value for octets

per frame (F) based on the JESD204B quick configuration

setting. K must also be a multiple of 4 and conform to the

following equation:

32 ≥ K ≥ Ceil (17/F)

•

The JESD204B specification also requires the number of

octets per multiframe (K × F) to be between 17 and 1024.

The F value is fixed through the quick configuration

setting to ensure that this relationship is true.

Table 11. JESD204B Configurable Identification Values

ID Value

Value Range

LID

0x67, [4:0]

0 to 31

DID

0x64, [7:0]

0 to 255

BID

0x65, [3:0]

0 to 15

Scramble, SCR.

•

Scrambling can be enabled or disabled by setting Address 0x6E,

Bit 7. By default, scrambling is enabled. Per the JESD204B

protocol, scrambling is functional only after the lane

synchronization has completed.

Select lane synchronization options.

Most of the synchronization features of the JESD204B interface

are enabled, by default, for typical applications. In some cases,

these features can be disabled or modified as follows:

•

ILAS enabling is controlled in Address 0x5F, Bits[3:2] and,

by default, is enabled. Optionally, to support some unique

instances of the interfaces (such as NMCDA-SL), the

JESD204B interface can be programmed to either disable the

ILAS sequence or continually repeat the ILAS sequence.

The AD9683 has fixed values of some of the JESD204B interface

parameters, and they are as follows:

•

N = 14, number of bits per converter is 14 in Address 0x72,

Bits[3:0]

•

N’ = 16, number of bits per sample is 16 in Address 0x73,

Bits[3:0]

•

CF = 0, number of control words per frame clock cycle per

converter is 0 in Address 0x75, Bits[4:0]

Verify read only values: lanes per link (L), octets per frame (F),

number of converters (M), and samples per converter per frame

(S). The AD9683 calculates values for some JESD204B parameters

based on other settings, particularly the quick configuration

•

L = lanes per link is 1; read the values from Address 0x6E,

Bits[4:0]

•

F = octets per frame is 1, 2, or 4; read the value from

Address 0x6F, Bits[7:0]

•

HD = high density mode can be 0 or 1; read the value from

Address 0x75, Bit 7

•

M = number of converters per link is 1; read the value from

Address 0x71, Bits[7:0]

•

S = samples per converter per frame can be 1 or 2; read the

value from Address 0x74, Bits[4:0]

Check FCHK, Checksum of JESD204B Interface Parameters

The JESD204B parameters can be verified through the checksum

value (FCHK) of the JESD204B interface parameters. Each lane has

a FCHK value associated with it. The FCHK value is transmitted

during the ILAS second multiframe and can be read from the

internal registers.

The checksum value is the modulo 256 sum of the parameters

listed in the No. column of Table 12. The checksum is calculated

by adding the parameter fields before they are packed into the

octets shown in Table 12.

The FCHK value for the lane configuration for data coming out

of the Lane 0 can be read from Address 0x79.

Table 12. JESD204B Configuration Table Used in ILAS and

CHKSUM Calculation

No.

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

DID[7:0]

BID[3:0]

LID[4:0]

SCR

L[4:0]

F[7:0]

K[4:0]

M[7:0]

CS[1:0]

N[4:0]

SUBCLASS[2:0]

N’[4:0]

JESDV[2:0]

S[4:0]

CF[4:0]

Set Additional Digital Output Configuration Options

Other data format controls include the following:

•

Invert polarity of serial output data, Address 0x60, Bit 1

•

ADC data format select (offset binary or twos complement),

Address 0x14, Bits[1:0]

•

Options for interpreting signal on SYSREF± and SYNCINB±,

Address 0x3A, Bits[4:0]

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