AD9683 datasheet(31/45 Pages) AD

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AD9683

Data Sheet

Rev. D | Page 30 of 44

Fast Threshold Detection (FD)

The FD indicator is asserted if the input magnitude exceeds the

value programmed in the fast detect upper threshold registers,

located in Address 0x47 and Address 0x48. The selected threshold

the ADC. The fast upper threshold detection has a latency of

seven clock cycles. The approximate upper threshold magnitude

is defined by

Upper Threshold Magnitude (dBFS) = 20 log (Threshold

Magnitude/213)

The FD indicators are not cleared until the signal drops below

the lower threshold for the programmed dwell time. The lower

threshold is programmed in the fast detect lower threshold

registers, located at Address 0x49 and Address 0x4A. The fast

detect lower threshold register is a 16-bit register that is compared

with the signal magnitude at the output of the ADC. This

comparison is subject to the ADC pipeline latency but is

accurate in terms of converter resolution. The lower threshold

magnitude is defined by

Lower Threshold Magnitude (dBFS) = 20 log (Threshold

Magnitude/213)

For example, to set an upper threshold of −6 dBFS, write

0x0FFF to those registers, and to set a lower threshold of

−10 dBFS, write 0x0A1D to those registers.

The dwell time can be programmed from 1 to 65,535 sample

clock cycles by placing the desired value in the fast detect dwell

time registers, located in Address 0x4B and Address 0x4C.

The operation of the upper threshold and lower threshold registers,

along with the dwell time registers, is shown in Figure 66.

UPPER THRESHOLD

LOWER THRESHOLD

DWELL TIME

TIMER RESET BY

RISE ABOVE

LOWER THRESHOLD

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE LT

DWELL TIME

Figure 66. Threshold Settings for FD Signals

AD9683 Datasheet(PDF) 31 Page - Analog Devices