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Data Sheet

AD10465

Rev. B | Page 13 of 24

APPLYING THE AD10465

ENCODING THE AD10465

The AD10465 encode signal must be a high quality, extremely

low phase noise source to prevent degradation of performance.

Maintaining 14-bit accuracy places a premium on encode clock

phase noise. SNR performance can easily degrade by 3 dB to

4 dB with 32 MHz input signals when using a high jitter clock

source. See the Analog Devices Application Note AN-501, Aper-

ture Uncertainty and ADC System Performance, for complete

details. For optimum performance, the AD10465 must be

clocked differentially. The encode signal is usually ac-coupled

into the ENCODE and ENCODE pins via a transformer or

capacitors. These pins are biased internally and require no

additional bias.

Figure 20 shows one preferred method for clocking the

AD10465. The clock source (low jitter) is converted from

single-ended to differential using an RF transformer. The back-

to-back Schottky diodes across the transformer secondary limit

clock excursions into the AD10465 to approximately 0.8 V p-p

differential. This helps prevent the large voltage swings of the

clock from feeding through to the other portions of the

AD10465, and limits the noise presented to the ENCODE

inputs. A crystal clock oscillator can also be used to drive the

RF transformer if an appropriate limiting resistor (typically

100 Ω) is placed in the series with the primary.

T1-4T

0.1nF

ENCODE

AD10465

HSMS2812

DIODES

CLOCK

SOURCE

100Ω

Figure 20. Crystal Clock Oscillator, Differential ENCODE

If a low jitter ECL/PECL clock is available, another option is to

ac couple a differential ECL/PECL signal to the ENCODE and

ENCODE input pins as shown in Figure 21. A device that offers

excellent jitter performance is the MC100LVEL16 (or same

family) from Motorola.

ENCODE

AD10465

0.1µF

ECL/

PECL

Figure 21. Differential ECL for ENCODE

JITTER CONSIDERATIONS

The signal-to-noise ratio (SNR) for an ADC can be predicted.

When normalized to ADC codes, Equation 1 accurately

predicts the SNR based on three terms. These are jitter, average

DNL error, and thermal noise. Each of these terms contributes

to the noise within the converter.



log









































 







rms

NOISE

ANALOG

rms

SNR





(1)

where:

fANALOG is the analog input frequency.

tj rms is the rms jitter of the encode (rms sum of encode source

and internal encode circuitry).

ε is the average DNL of the ADC (typically 0.50 LSB).

N is the number of bits in the ADC.

VNOISE rms is the V rms noise referred to the analog input of the

ADC (typically 5 LSB).

For a 14-bit analog-to-digital converter like the AD10465,

aperture jitter can greatly affect the SNR performance as the

analog frequency is increased. The chart below shows a family

of curves that demonstrates the expected SNR performance of

the AD10465 as jitter increases. The chart is derived from

Equation 1.

For a complete discussion of aperture jitter, please consult the

Analog Devices Application Note AN-501, Aperture Uncertainty

and ADC System Performance.

RMS CLOCK JITTER (ps)

AIN = 5MHz

AIN = 10MHz

AIN = 20MHz

AIN = 32MHz

Figure 22. SNR vs. Jitter

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