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LTC3416

3416f

APPLICATIO S I FOR ATIO

Soft-Start

The RUN/SS pin provides a means to shut down the

LTC3416 as well as a timer for soft-start. Pulling the RUN/

SS pin below 0.5V places the LTC3416 in a low quiescent

current shutdown state (IQ < 1µA).

The soft-start gradually raises the clamp on ITH. The full

current range becomes available on ITH after the voltage

on ITH reaches approximately 2V. The clamp on ITH is set

externally with a resistor and capacitor on the RUN/SS pin

as shown in Figure 1a. The soft-start duration can be

calculated by using the following formula:

tR C In

Seconds

SS SS









–.

()

Efficiency Considerations

The efficiency of a switching regulator is equal to the

output power divided by the input power times 100%. It is

often useful to analyze individual losses to determine what

is limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as:

Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percentage

of input power.

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

losses: VIN quiescent current and I2R losses.

The VIN quiescent current loss dominates the efficiency

loss at very low load currents whereas the I2R loss

dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve at

very low load currents can be misleading since the actual

power lost is of no consequence.

1. The VIN quiescent current is due to two components:

the DC bias current as given in the electrical character-

istics and the internal main switch and synchronous

switch gate charge currents. The gate charge current

results from switching the gate capacitance of the

internal power MOSFET switches. Each time the gate is

switched from high to low to high again, a packet of

charge dQ moves from VIN to ground. The resulting

dQ/dt is the current out of VIN that is typically larger

than the DC bias current. In continuous mode, IGATECHG

= f(QT + QB) where QT and QB are the gate charges of

the internal top and bottom switches. Both the DC bias

and gate charge losses are proportional to VIN and thus

their effects will be more pronounced at higher supply

voltages.

2. I2R losses are calculated from the resistances of the

internal switches, RSW, and external inductor RL. In

continuous mode the average output current flowing

through inductor L is “chopped” between the main

switch and the synchronous switch. Thus, the series

resistance looking into the SW pin is a function of both

top and bottom MOSFET RDS(ON) and the duty cycle

(DC) as follows:

RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC)

The RDS(ON) for both the top and bottom MOSFETs can

be obtained from the Typical Performance Characteris-

tics curves. Thus, to obtain I2R losses, simply add RSW

to RL and multiply the result by the square of the

average output current.

Other losses including CIN and COUT ESR dissipative

losses and inductor core losses generally account for less

than 2% of the total loss.

In most applications, the LTC3416 does not dissipate

much heat due to its high efficiency. But in applications

where the LTC3416 is running at high ambient tempera-

ture with low supply voltage and high duty cycles, such as

Figure 5. Dual Voltage System with Tracking

LTC3416

SGND

3416 F05

VFB

TRACK

VOUT1

LTC3416

SLAVE

MASTER

SGND

VFB

VOUT2

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