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AD6655 Datasheet(PDF) 52 Page - Analog Devices |
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AD6655 Datasheet(HTML) 52 Page - Analog Devices |
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52 / 85 page ![]() Data Sheet AD6655 Rev. B | Page 51 of 84 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 29 are not currently supported for this device. Table 29. Memory Map Registers Addr. (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments Chip Configuration Registers 0x00 SPI Port Configuration (Global) 0 LSB first Soft reset 1 1 Soft reset LSB first 0 0x18 The nibbles are mirrored so that LSB-first or MSB-first mode registers correctly, regardless of shift mode 0x01 Chip ID (Global) 8-bit Chip ID[7:0] (AD6655 = 0x0D) (default) 0x0D Default is unique chip ID, different for each device; this is a read-only register 0x02 Chip Grade (Global) Open Open Speed Grade ID[4:3] 00 = 150 MSPS 01 = 125 MSPS 10 = 105 MSPS 11 = 80 MSPS Open Open Open Open Speed grade ID used to differentiate devices; this is a read-only register Channel Index and Transfer Registers 0x05 Channel Index Open Open Open Open Open Open Data Channel B (default) Data Channel A (default) 0x03 Bits are set to determine which device on chip receives the next write command; applies to local registers 0xFF Transfer Open Open Open Open Open Open Open Transfer 0x00 Synchronously transfers data from the master shift register to the slave ADC Function Registers 0x08 Power Modes Open Open External power- down pin function (global) 0 = pdwn 1 = stndby Open Open Open Internal power-down mode (local) 00 = normal operation 01 = full power-down 10 = standby 11 = normal operation 0x00 Determines various generic modes of chip operation 0x09 Global Clock (Global) Open Open Open Open Open Open Open Duty cycle stabilize (default) 0x01 0x0B Clock Divide (Global) Open Open Open Open Open Clock divide ratio 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 Clock divide values other than 000 automatically activate duty cycle stabilization |
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