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AD6655 Datasheet(PDF) 16 Page - Analog Devices |
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AD6655 Datasheet(HTML) 16 Page - Analog Devices |
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16 / 85 page  Data Sheet AD6655 Rev. B | Page 15 of 84 TIMING SPECIFICATIONS Table 9. Parameter Conditions Min Typ Max Unit SYNC TIMING REQUIREMENTS tSSYNC SYNC to the rising edge of CLK setup time 0.24 ns tHSYNC SYNC to the rising edge of CLK hold time 0.4 ns SPI TIMING REQUIREMENTS tDS Setup time between the data and the rising edge of SCLK 2 ns tDH Hold time between the data and the rising edge of SCLK 2 ns tCLK Period of the SCLK 40 ns tS Setup time between CSB and SCLK 2 ns tH Hold time between CSB and SCLK 2 ns tHIGH Minimum period that SCLK should be in a logic high state 10 ns tLOW Minimum period that SCLK should be in a logic low state 10 ns tEN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge 10 ns tDIS_SDIO Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 10 ns SPORT TIMING REQUIREMENTS tCSSCLK Delay from rising edge of CLK+ to rising edge of SMI SCLK 3.2 4.5 6.2 ns tSSLKSDO Delay from rising edge of SMI SCLK to SMI SDO −0.4 0 +0.4 ns tSSCLKSDFS Delay from rising edge of SMI SCLK to SMI SDFS −0.4 0 +0.4 ns Timing Diagrams tH tS CLK+ DECIMATED CMOS DATA DECIMATED FD DATA CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS CHANNEL A/B FD BITS DECIMATED DCOA/DCOB tPD tDCO Figure 2. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000) tS tPD tDCO tH CLK+ DECIMATED CMOS DATA CHANNEL A/B DATA BITS CHANNEL A/B DATA BITS DECIMATED FD DATA CHANNEL A/B FD BITS CHANNEL A/B FD BITS DECIMATED DCOA/DCOB CHANNEL A/B DATA BITS CHANNEL A/B FD BITS Figure 3. Decimated Noninterleaved CMOS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100) |
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