AD6655 datasheet(56/85 Pages) AD

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Data Sheet

AD6655

Rev. B | Page 55 of 84

MEMORY MAP REGISTER DESCRIPTION

For more information on functions controlled in Register 0x00

to Register 0xFF, see Application Note AN-877, Interfacing to

High Speed ADCs via SPI, at www.analog.com. Note that not all

test modes are supported on the AD6655.

SYNC Control (Register 0x100)

Bit 7—Signal Monitor Sync Enable

Bit 7 enables the sync pulse from the external sync input to the

signal monitor block. The sync signal is passed when Bit 7 and

Bit 0 are high. This is continuous sync mode.

Bit 6—Half-Band Next Sync Only

If the master sync enable bit (Register 0x100, Bit 0) and the half-

band sync enable bit (Register 0x100, Bit 5) are high, Bit 6 allows

the NCO32 to synchronize following the first sync pulse it

receives and ignore the rest. If Bit 6 is set, Bit 5 of Register

0x100 resets after this sync occurs.

Bit 5—Half-Band Sync Enable

Bit 5 gates the sync pulse to the half-band filter. When Bit 5

is set high, the sync signal causes the half-band to resynchro-

nize, starting at the half-band decimation phase selected in

sync enable bit (Register 0x100, Bit 0) is high. This is continuous

sync mode.

Bit 4—NCO32 Next Sync Only

If the master sync enable bit (Register 0x100, Bit 0) and the

NCO32 sync enable bit (Register 0x100, Bit 3) are high, Bit 4

allows the NCO32 to synchronize following the first sync pulse it

receives and ignore the rest. Bit 3 of Register 0x100 resets after

a sync occurs if Bit 4 is set.

Bit 3—NCO32 Sync Enable

Bit 3 gates the sync pulse to the 32-bit NCO. When this bit is set

high, the sync signal causes the NCO to resynchronize, starting

at the NCO phase offset value. This sync is active only when the

master sync enable bit (Register 0x100, Bit 0) is high. This is

continuous sync mode.

Bit 2—Clock Divider Next Sync Only

If the master sync enable bit (Register 0x100, Bit 0) and the

clock divider sync enable bit (Register 0x100, Bit 1) are high,

Bit 2 allows the clock divider to synchronize following the first

sync pulse it receives and ignores the rest. Bit 1 of Register 0x100

resets after it synchronizes.

Bit 1—Clock Divider Sync Enable

Bit 1 gates the sync pulse to the clock divider. The sync signal

is passed when Bit 1 and Bit 0 are high. This is continuous

sync mode.

Bit 0—Master Sync Enable

Bit 0 must be high to enable any of the sync functions.

fS/8 Output Mix Control (Register 0x101)

Bits[7:6]—Reserved

Bits[5:4]—fS/8 Start State

Bit 5 and Bit 4 set the starting phase of the fS/8 output mix.

Bits[3:2]—Reserved

Bit 1—fS/8 Next Sync Only

If the master sync enable bit (Register 0x100, Bit 0) and the fS/8

sync enable bit (Register 0x101, Bit 0) are high, Bit 1 allows the

fS/8 output mix to synchronize following the first sync pulse it

receives and ignore the rest. Bit 0 of Register 0x100 resets after it

synchronizes.

Bit 0—fS/8 Sync Enable

Bit 0 gates the sync pulse to the fS/8 output mix. This sync is

active only when the master sync enable bit (Register 0x100,

Bit 0) is high. This is continuous sync mode.

FIR Filter and Output Mode Control (Register 0x102)

Bits[7:4]—Reserved

Bit 3—FIR Gain

When Bit 3 is set high, the FIR filter path, if enabled, has a gain

of 1. When Bit 3 set low, the FIR filter path has a gain of 2.

Bit 2—fS/8 Output Mix Disable

Bit 2 disables the fS/8 output mix when enabled. Bit 2 should be

set along with Bit 1 to enable complex output mode.

Bit 1—Complex Output Mode Enable

Setting Bit 1 high enables complex output mode.

Bit 0—FIR Filter Enable

When set high, Bit 0 enables the FIR filter. When Bit 0 is

cleared, the FIR filter is bypassed and shut down for power

savings.

AD6655 Datasheet(PDF) 56 Page - Analog Devices

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