AD6655 datasheet(33/85 Pages) AD

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AD6655

Data Sheet

Rev. B | Page 32 of 84

If the internal reference of the AD6655 is used to drive multiple

converters to improve gain matching, the loading of the reference

by the other converters must be considered. Figure 54 depicts

how the internal reference voltage is affected by loading.

–1.25

2.0

LOAD CURRENT (mA)

–0.25

–0.50

–0.75

–1.00

0.5

1.0

1.5

VREF = 0.5V

VREF = 1.0V

Figure 54. VREF Accuracy vs. Load

External Reference Operation

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift charac-

teristics. Figure 55 shows the typical drift characteristics of the

internal reference in both 1.0 V and 0.5 V modes.

2.5

–2.5

–40

TEMPERATURE (°C)

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

–20

Figure 55. Typical VREF Drift

When the SENSE pin is tied to AVDD, the internal reference is

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

6 kΩ load (see Figure 18). The internal buffer generates the positive

and negative full-scale references for the ADC core. Therefore,

the external reference must be limited to a maximum of 1.0 V.

CLOCK INPUT CONSIDERATIONS

For optimum performance, the AD6655 sample clock inputs,

CLK+ and CLK−, should be clocked with a differential signal.

The signal is typically ac-coupled into the CLK+ and CLK− pins

via a transformer or capacitors. These pins are biased internally

(see Figure 56) and require no external bias.

1.2V

AVDD

2pF

CLK–

CLK+

Figure 56. Equivalent Clock Input Circuit

Clock Input Options

The AD6655 has a very flexible clock input structure. Clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter

is of the most concern, as described in the Jitter Considerations

section.

Figure 57 and Figure 58 show two preferred methods for clocking

the AD6655 (at clock rates to up to 625 MHz). A low jitter clock

source is converted from a single-ended signal to a differential

signal using an RF transformer. The back-to-back Schottky diodes

across the transformer secondary limit clock excursions into the

AD6655 to approximately 0.8 V p-p differential. This helps prevent

the large voltage swings of the clock from feeding through to other

portions of the AD6655, while preserving the fast rise and fall times

of the signal, which are critical to a low jitter performance.

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLOCK

INPUT

50Ω

100Ω

CLK–

CLK+

ADC

AD6655

Mini-Circuits®

ADT1–1WT, 1:1Z

XFMR

Figure 57. Transformer Coupled Differential Clock (Up to 200 MHz)

0.1µF

1nF

CLOCK

INPUT

1nF

50Ω

CLK–

CLK+

ADC

AD6655

SCHOTTKY

DIODES:

HSMS2822

Figure 58. Balun-Coupled Differential Clock (Up to 625 MHz)

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins as shown in Figure 59. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent

jitter performance.

AD6655 Datasheet(PDF) 33 Page - Analog Devices

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