AD7192 datasheet(33/41 Pages) AD

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AD7192

Rev. A | Page 32 of 40

CIRCUIT DESCRIPTION

ANALOG INPUT CHANNEL

The AD7192 has two differential/four pseudodifferential analog

input channels, which can be buffered or unbuffered. In buffered

mode (the BUF bit in the configuration register is set to 1), the

input channel feeds into a high impedance input stage of the

buffer amplifier. Therefore, the input can tolerate significant

source impedances and is tailored for direct connection to

external resistive-type sensors such as strain gages or resistance

temperature detectors (RTDs).

When BUF = 0, the part is operated in unbuffered mode. This

results in a higher analog input current. Note that this unbuffered

input path provides a dynamic load to the driving source.

Therefore, resistor/capacitor combinations on the input pins

can cause gain errors, depending on the output impedance of

the source that is driving the ADC input. Table 22 shows the

allowable external resistance/capacitance values for unbuffered

mode at a gain of 1 such that no gain error at the 20-bit level is

introduced.

Table 22. External R-C Combination for No 20-Bit Gain Error

C (pF)

R (Ω)

1.4 k

100

850

500

300

1000

230

5000

The absolute input voltage range in buffered mode is restricted

to a range between AGND + 250 mV and AVDD − 250 mV. Care

must be taken in setting up the common-mode voltage so that

these limits are not exceeded. Otherwise, there is degradation in

linearity and noise performance.

The absolute input voltage in unbuffered mode includes the

range between AGND − 50 mV and AVDD + 50 mV. The

negative absolute input voltage limit does allow the possibility

of monitoring small true bipolar signals with respect to AGND.

PROGRAMMABLE GAIN ARRAY (PGA)

When the gain stage is enabled, the output from the buffer is

applied to the input of the PGA. The presence of the PGA

means that signals of small amplitude can be gained within the

AD7192 while still maintaining excellent noise performance.

For example, when the gain is set to 128, the rms noise is 11 nV,

typically, when the output data rate is 4.7 Hz, which is equivalent

to 22.5 bits of effective resolution or 20 bits of noise-free

resolution.

The AD7192 can be programmed to have a gain of 1, 8, 16, 32,

64, and 128 using Bit G2 to Bit G0 in the configuration register.

Therefore, with an external 2.5 V reference, the unipolar ranges

are from 0 mV to 19.53 mV to 0 V to 2.5 V and the bipolar

ranges are from ±19.53 mV to ±2.5 V.

The analog input range must be limited to ±(AVDD – 1.25 V)/gain

because the PGA requires some headroom. Therefore, if AVDD =

5 V, the maximum analog input that can be applied to the

AD7192 is 0 to 3.75 V/gain in unipolar mode or ±3.75 V/gain

in bipolar mode.

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7192 can accept either unipolar or

bipolar input voltage ranges. A bipolar input range does not

imply that the part can tolerate negative voltages with respect to

system AGND. In pseudo-differential mode, signals are

referenced to AINCOM, while in differential mode, signals are

referenced to the negative input of the differential pair. For

example, if AINCOM is 2.5 V and the AD7192 AIN1 analog

input is configured for unipolar mode with a gain of 2, the input

voltage range on the AIN1 pin is 2.5 V to 3.75 V when a 2.5 V

reference is used.

If AINCOM is 2.5 V and the AD7192 AIN1 analog input is

configured for bipolar mode with a gain of 2, the analog input

range on AIN1 is 1.25 V to 3.75 V The bipolar/unipolar option

is chosen by programming the U/B bit in the configuration

DATA OUTPUT CODING

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage resulting in a code of 00...00, a midscale voltage result-

ing in a code of 100...000, and a full-scale input voltage resulting

in a code of 111...111. The output code for any analog input

voltage can be represented as

Code = (2N × AIN × Gain)/VREF

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000...000, a zero differential input voltage resulting

in a code of 100...000, and a positive full-scale input voltage

resulting in a code of 111...111. The output code for any analog

input voltage can be represented as

Code = 2N – 1 × [(AIN × Gain/VREF) + 1]

where AIN is the analog input voltage, Gain is the PGA setting

(1 to 128), and N = 24.

CLOCK

The AD7192 includes an internal 4.92 MHz clock on-chip. This

internal clock has a tolerance of ±4%. Either the internal clock

or an external crystal/clock can be used as the clock source to

the AD7192. The clock source is selected using the CLK1 and

CLK0 bits in the mode register. When an external crystal is

used, it must be connected across the MCLK1 and MCLK2

pins. The crystal manufacturer recommends the load capacitances

required for the crystal. The MCLK1 and MCLK2 pins of the

AD7192 have a capacitance of 15 pF, typically. If an external

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