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AD7291

Data Sheet

Rev. C | Page 18 of 28

Table 12. Channel Selection Bits for Command Register

D15

D14

D13

D12

D11

D10

Selected Analog Input Channel

Comments

No channel selected

If more than one channel is

selected, the AD7291 converts the

selected channels starting with the

lowest channel in the sequence.

Convert on Channel 7 (VIN7)

Convert on Channel 6 (VIN6)

Convert on Channel 5 (VIN5)

Convert on Channel 4 (VIN4)

Convert on Channel 3 (VIN3)

Convert on Channel 2 (VIN2)

Convert on Channel 1 (VIN1)

Convert on Channel 0 (VIN0)

Table 13. TSENSE Data Format

Input

D11 (MSB)

D10

D0 (LSB)

Value (°C)

−512

+256

+128

+64

+32

+16

+0.5

+0.25

Sample Delay and Bit Trial Delay

Ideally, no I2C bus activity must occur while an ADC conversion is

taking place. However, this cannot be possible, for example, when

operating in autocycle mode. It is therefore recommended to

enable the noise delayed bit trial and sampling function by writing

a 1 to Bit D5 in the command register. This mechanism delays

critical sample intervals and bit trials while there is activity on

the I2C bus. This results in a quiet period for each bit decision,

and conversion results are less susceptible to interference from

external noise.

On power-up, the bit trial and sample interval delay mechanism

is not enabled. It is recommended that this feature must be

enabled for normal operation. When enabled, the AD7291

delays the bit trials, mitigating against the effect of activity on

the I2C bus. In cases where there is excessive activity on the

interface lines, enabling these bits can cause the overall

conversion time to increase.

The AD7291 also incorporates functionality that allows it to

reject glitches shorter than 50 ns. This feature improves the

noise susceptibility of the device.

VOLTAGE CONVERSION RESULT REGISTER (0x01)

The voltage conversion result register is a 16-bit read-only

straight binary format. A 2-byte read is necessary to read data

from this register. Table 14 and Table 15 show the contents of

the first and second bytes of data to be read from the AD7291.

Each AD7291 conversion result consists of four channel address

bits (see Table 14 and Table 15) and the 12-bit data result.

Bit D15 to Bit D12 are the channel address bits that identify

the ADC channel that corresponds to the subsequent result.

Bit D11 to Bit D0 contain the most recent ADC result.

Table 14. Conversion Value Register (First Read)

MSB

D15

D14

D13

D12

D11

D10

ADD3

ADD2

ADD1

ADD0

B11

B10

Table 15. Conversion Value Register (Second Read)

LSB

Table 16. Channel Address Bits for the Result Register

ADD2

ADD1

ADD0

Analog Input Channel

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

TSENSE

TSENSE average result

Temperature Value Format

The temperature reading from the ADC is stored in an 11-bit

twos complement format, D11 to D0, to accommodate both

positive and negative temperature measurements. The tem-

perature data format is provided in Table 13.

TSENSE CONVERSION RESULT REGISTER (0x02)

The TSENSE result register is a 16-bit read-only register used to

store the ADC data generated from the internal temperature

sensor. This register stores the temperature readings from the

ADC in a 12-bit twos complement format, D11 to D0, and

uses Bit D15 to Bit D12 to store the channel address bits.

Conversions take place approximately every 5 ms. Table 13

details the temperature data format that applies to the internal

temperature sensor.

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