Preliminary Technical Data

AD5662

Rev. PrA | Page 13 of 20

GENERAL DESCRIPTION

D/A SECTION

The AD5662 DAC is fabricated on a CMOS process. The

architecture consists of a string DAC followed by an output

buffer amplifier. Figure 27 shows a block diagram of the DAC

architecture.

GND

RESISTOR

STRING

REF (+)

REF (–)

OUTPUT

AMPLIFIER

DAC REGISTER

Figure 27. DAC Architecture

Since the input coding to the DAC is straight binary, the ideal

output voltage is given by

⎟

⎠

⎞

⎜

⎝

⎛

×

=

536

,

65

D

VREF

V

OUT

where D is the decimal equivalent of the binary code that is

loaded to the DAC register; it can range from 0 to 65535.

RESISTOR STRING

The resistor string section is shown in Figure 28. It is simply a

string of resistors, each of value R. The code loaded to the DAC

register determines at which node on the string the voltage is

tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. Because it is a string of resistors, it is guaranteed

monotonic.

R

R

R

R

R

TO OUTPUT

AMPLIFIER

Figure 28. Resistor String

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating rail-to-rail

voltages on its output which gives an output range of 0 V to

pF to GND. The source and sink capabilities of the output

amplifier can be seen in Figure 10 and Figure 11. The slew rate

is 1 V/µs with a half-scale settling time of 8 µs with the output

unloaded.

SERIAL INTERFACE

The AD5662 has a 3-wire serial interface (SYNC, SCLK, and

DIN) that is compatible with SPI, QSPI, and MICROWIRE

interface standards as well as most DSPs. See Figure 2 for a

timing diagram of a typical write sequence.

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 24-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 30 MHz, making the AD5662compatible with high speed

in and the programmed function is executed (i.e., a change in

DAC register contents and/or a change in the mode of operation).

At this stage, the SYNC line may be kept low or be brought

high. In either case, it must be brought high for a minimum of

33 ns before the next write sequence so that a falling edge of

SYNC can initiate the next write sequence. Since the SYNC

for even lower power operation. As is mentioned previously,

however, it must be brought high again just before the next

write sequence.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 29). The first

six bits are don’t cares. The next two are control bits that control

the part’s mode of operation (normal mode or any one of three

power-down modes). See the Power-On Reset section for a

more complete description of the various modes. The next 16

bits are the data bits. These are transferred to the DAC register

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 24 falling edges of SCLK, and the DAC is updated on the

The shift register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs—see Figure 30.