AD5662ARM datasheet(3/20 Pages) AD

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Preliminary Technical Data

AD5662

Rev. PrA | Page 3 of 20

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREF = VDD: all specifications TMIN to TMAX, unless otherwise noted.

Table 1.

A Grade

B Grade

B Version1

Parameter

Min

Typ

Max

Min

Typ

Max

Unit

Conditions/Comments

STATIC PERFORMANCE2

Resolution

Bits

Relative Accuracy

±32

±16

LSB

See Figure 4.

Differential Nonlinearity

±1

LSB

Guaranteed monotonic by design.

See Figure 5.

Zero Code Error

All 0s loaded to DAC register. See Figure 8.

Full-Scale Error

−0.15

−1.25

−0.15

−1.25

% FSR

All 1s loaded to DAC register. See Figure 8.

Offset Error

±10

Gain Error

±1.25

% FSR

Zero Code Error Drift3

±2

µV/°C

Gain Temperature Coefficient3

±2.5

ppm

Of FSR/°C

DC Power Supply Rejection

Ratio

-100

DAC code = midscale; VDD = 5V/3V ±10%

OUTPUT CHARACTERISTICS3

Output Voltage Range

VDD

Output Voltage Settling Time

µs

¼ to ¾ scale;

RL = 2 kΩ; 0 pF < CL < 200 pF. See Figure 18.

µs

1 LSB Settling

Slew Rate

1.5

V/µs

¼ to ¾ scale

Capacitive Load Stability

RL = ∞

RL = 2 kΩ

Output Noise Spectral Density

nV/√Hz

DAC code = midscale,10 kHz

Output Noise (0.1 Hz to 10 Hz)

µVp-p

DAC code = midscale

THD, Total Harmonic Distortion

-80

VREF = 2 V ± 300 mV p-p, f = 5 kHz

Digital-to-Analog Glitch Impulse

nV-s

1 LSB change around major carry.

See Figure 21.

Digital Feedthrough

0.1

nV-s

DC Output Impedance

0.5

Ω

Short-Circuit Current4

VDD = 5 V, 3 V

Power-Up Time

µs

Coming out of power-down mode. VDD = 5 V

µs

VDD = 3 V

REFERENCE INPUTS

Reference Current

µA

VREF = VDD = 5 V

µA

VREF = VDD = 3.6 V

Reference Input Range

VDD

Reference Input Impedance

150

kΩ

LOGIC INPUTS3

Input Current

±1

µA

VINL, Input Low Voltage

0.8

VDD = 5 V, 3 V

VINH, Input High Voltage

VDD = 5 V, 3 V

Pin Capacitance

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