AD5662ARM datasheet(14/20 Pages) AD

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AD5662

Preliminary Technical Data

Rev. PrA | Page 14 of 20

DATA BITS

DB23 (MSB)

DBO (LSB)

PD1

PD0

D13

D12

D11

D10

NORMAL OPERATION

1 k

Ω TO GND

100 k

Ω TO GND

THREE-STATE

POWER-DOWN MODES

Figure 29. Input Register Contents

DIN

DB23

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24TH FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 24TH FALLING EDGE

SYNC

SCLK

Figure 30. SYNC Interrupt Facility

POWER-ON RESET

The AD5662 family contains a power-on-reset circuit that

controls the output voltage during power-up. The AD5662x-1

DAC output powers up to 0 V, and the AD5662x-2 DAC output

powers up to midscale. The output remains there until a valid

write sequence is made to the DAC. This is useful in

applications where it is important to know the state of the

output of the DAC while it is in the process of powering up.

POWER-DOWN MODES

The AD5662 contains four separate modes of operation. These

modes are software-programmable by setting two bits (DB17

and DB16) in the control register. Table 5 shows how the state

of the bits corresponds to the device’s mode of operation.

Table 5. Modes of Operation for the AD5662

DB17

DB16

Operating Mode

Normal Operation

Power-Down Modes

1 kΩ to GND

100 kΩ to GND

Three-State

When both bits are set to 0, the part works normally with its

normal power consumption of 250 µA at 5 V. However, for the

three power-down modes, the supply current falls to 200 nA at

5 V (50 nA at 3 V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different

options. The output is connected internally to GND through a

1 kΩ or 100 kΩ resistor, or is left open-circuited (three-state).

The output stage is illustrated in Figure 31.

RESISTOR

NETWORK

VOUT

VFB

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 31. Output Stage during Power-Down

The bias generator, the output amplifier, the resistor string, and

other associated linear circuitry are all shut down when the

power-down mode is activated. However, the contents of the

DAC register are unaffected when in power-down. The time to

exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs for

VDD = 3 V. See Figure 20 for a plot.

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