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AD7732

CIRCUIT DESCRIPTION

The AD7732 is a sigma-delta ADC that is intended for the

measurement of wide dynamic range, low frequency signals in

industrial process control, instrumentation, and PLC systems.

It contains thin film resistor dividers, a multiplexer, an input

buffer, a sigma-delta (or charge balancing) ADC, a digital filter,

a clock oscillator, a digital I/O port, and a serial

communications interface.

Analog Front End

The AD7732 features two fully differential analog inputs. The

on-chip thin film resistor dividers allow ±10 V, ±5 V, 0 V to +10

V, and 0 V to +5 V input signals to be connected directly to the

analog input pins.

The resistor divider input stage is followed by the multiplexer

and then by a wide bandwidth, fast settling time differential

input buffer capable of driving the dynamic load of a high speed

sigma-delta modulator.

In normal circuit configuration, the BIAS pins are connected to

the 2.5 V (reference) voltage source. This ensures that the

differential signal seen by the internal input buffer is within its

absolute/common-mode range of AGND + 200 mV to

AVDD – 300 mV.

The AD7732 AIN differential voltage should be within the

specified nominal (up to ±10 V) input range, otherwise the

performance on channel might degrade (see the Analog Input’s

Extended Voltage Range section).

The AD7732 INL performance varies with the AIN common-

mode voltage (Figure 9). The differential analog input voltage of

±10 V with a common-mode voltage of 0 V means that the AIN

differential voltage is centered around AGND and both AIN(+)

and AIN(–) change within ±5 V respect to AGND. The AD7732

INL also varies with the MCLK frequency (Figure 7).

If the BIAS pins are in normal configuration, the AIN pin

absolute voltage up to ±16.5 V does not degrade the adjacent

channel’s performance. An AIN absolute voltage over ±16.5 V

results in current flowing through the internal protection

diodes located behind the thin film resistors; the adjacent

channel can be affected. By configuring the BIAS and RA to RD

pins differently, the part will work with higher AIN absolute

voltages as long as the internal voltage seen by the multiplexer

and input buffer is within 200 mV to AVDD – 300 mV. Absolute

voltage for the AIN, BIAS, and RA to RD pins must never

exceed the values specified in the Absolute Maximum Ratings.

Note that the OVR bit in the channel status register is generated

digitally from the conversion result and indicates the sigma-

delta modulator (nominal) overrange. The OVR bit DOES NOT

indicate exceeding the AIN pin absolute/common-mode

voltage limits.

Figure 23 shows the AD7732 analog input internal structure.

BIAS

AIN

108.5k

Ω

15.5k

Ω

AVDD

MUX

PROTECTION

DIODES

AGND

2.1875V ± 1.25V

2.5V

±10V

BUFFER

Figure 23. Simplified Analog Input Internal Structure

Rev. 0 | Page 26 of 32

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