AMERICAN MICROSYSTEMS, INC.

September 2000

9.18.00

5

FS6232-01

FS6232-01

FS6232-01

FS6232-01

Two-Way MP Motherboard Clock Generator IC

Two-Way MP Motherboard Clock Generator IC

Two-Way MP Motherboard Clock Generator IC

Two-Way MP Motherboard Clock Generator IC

ISO9001

ISO9001

ISO9001

ISO9001

4.0

Power Management

The PWR_DWN# signal is an asynchronous, active-low

LVTTL input that places the device in a low power inac-

tive state without removing power from the device. All

internal clocks are turned off, and all clock outputs are

held low.

Since PWR_DWN# is asynchronous, the signal is syn-

chronized internally to each individual clock. As shown in

Figure 3, a falling-rising-falling edge sequence on any

individual clock output is required before that clock output

is disabled low. This edge sequence ensures that one

complete clock cycle will occur before the clock stops.

Table 9: Latency Table

LATENCY

SIGNAL

SIGNAL

STATE

MIN.

MAX.

Output:

2 clocks

3 clocks

0

Power

OFF

Device:

2

× REF

clocks

3

× REF clocks

PWR_

DWN#

1

Power

ON

3ms

Upon the release of PWR_DWN# (power-up), external

circuitry should allow a minimum of 3ms for the PLL to

lock before enabling any clocks.

Figure 3: PWR_DWN# Timing

Any Clock

(output)

PWR_DWN#

Any Clock

(internal)

VCO

Crystal

Oscillator

After REF

output shuts off...

3ms until clock is valid

Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active.

5.0

Dual Function I/O Pins

Several pins on this device serve as dual function in-

put/output pins. During the initial application of VDD to

the device, this type of pin functions as an input pin.

Upon completion of power-up, the logic state present on

the pin is latched internally, and the pin is converted to an

output driver.

An external 10kΩ pull-down resistor to ground is required

for a logic low and a 10kΩ pull-up resistor to the clock

output VDD is required for a logic high. The 10kΩ resistor

presents an insignificant load to the output driver that

should not affect the output clock.

Note that the latching of the logic state occurs only on the

application of the chip supply voltage (VDD). The logic

state on the pin is not latched if the PWR_DWN# signal is

used to power-down the device with VDD still applied.

Figure 4: I/O Pin Programming

Clock Trace

Termination

Resistor

Device Solder

Pads

Ground or

Power Via

10k

Ω

Programming

Resistor