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FS6232-01 Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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FS6232-01 Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
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9 / 14 page ![]() AMERICAN MICROSYSTEMS, INC. September 2000 9.18.00 9 FS6232-01 FS6232-01 FS6232-01 FS6232-01 Two-Way MP Motherboard Clock Generator IC Two-Way MP Motherboard Clock Generator IC Two-Way MP Motherboard Clock Generator IC Two-Way MP Motherboard Clock Generator IC ISO9001 ISO9001 ISO9001 ISO9001 Table 14: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σfrom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Spread Spectrum Modulation Frequency * fm SS_EN# low 31.5 kHz Spread Spectrum Modulation Index * δm SS_EN# low -0.5 % Clock Offset tpd CK66 leads @ 1.5V, CL=30pF to PCI @ 1.5V, CL = 30pF (measured on rising edges) 1.5 3.5 ns Output Tristate Enable Delay * tDZL, tDZH SEL_A:B = 00, SEL133/100# = 0 1.0 10 ns Output Tristate Disable Delay * tDLZ, tDHZ SEL_A:B = 11, SEL133/100# = 0 1.0 10 ns Power-up PLL Lock Time tL via PWR_DWN# 3.0 ms HOST_P1:4, HOST_N1:4 Clock Outputs Clock Skew * tsk(o) HOST pair to HOST pair @ VX, RIREF = 475 Ω, IOH = 6 × IREF, RS = 33.2Ω, RP = 49.9Ω 150 ps Duty Cycle * dt Ratio of high pulse width to one clock period at VX, RIREF = 475 Ω, IOH = 6 × IREF, RS=33.2Ω, RP=49.9Ω 45 55 % Jitter, Period (peak-peak) * tj(∆P) Rising edge to rising edge at VX, RIREF = 475 Ω, IOH = 6 × IREF RS = 33.2Ω, RP = 49.9Ω 200 ps Rise Time * tr Measured at 20% – 80% of VOH; RIREF = 475 Ω, IOH = 6 × IREF RS = 33.2Ω, RP = 49.9Ω 175 450 ps Rise/Fall Time Matching* Measured at 20% – 80% of VOH; RIREF = 475 Ω, IOH = 6 × IREF RS = 33.2Ω, RP = 49.9Ω 20 % MREF_P, MREF_N Clock Outputs Duty Cycle * dt Ratio of high pulse width to one clock period, measured at 1.5V 45 55 % Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL=30pF 250 ps tr min Measured @ 0.4V – 2.4V; CL=10pF 0.4 Rise Time * tr max Measured @ 0.4V – 2.4V; CL=30pF 1.6 ns tf min Measured @ 2.4V – 0.4V; CL=10pF 0.4 Fall Time * tf max Measured @ 2.4V – 0.4V; CL=30pF 1.6 ns |
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