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FS6232-01 Datasheet(PDF) 10 Page - List of Unclassifed Manufacturers |
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FS6232-01 Datasheet(HTML) 10 Page - List of Unclassifed Manufacturers |
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10 / 14 page  AMERICAN MICROSYSTEMS, INC. September 2000 9.18.00 10 FS6232-01 FS6232-01 FS6232-01 FS6232-01 Two-Way MP Motherboard Clock Generator IC Two-Way MP Motherboard Clock Generator IC Two-Way MP Motherboard Clock Generator IC Two-Way MP Motherboard Clock Generator IC ISO9001 ISO9001 ISO9001 ISO9001 Table 15: AC Timing Specifications, continued Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are ± 3σfrom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS PCI_0:9 Clock Outputs Duty Cycle * dt Ratio of high pulse width to one clock period, measured at 1.5V 45 55 % Clock Skew * tsk(o) One clock output relative to another at 1.5V 500 ps Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 30pF 500 ps tr min Measured at 0.4V – 2.4V; CL = 10pF 0.5 Rise Time * tr max Measured at 0.4V – 2.4V; CL = 30pF 2.0 ns tf min Measured at 2.4V – 0.4V; CL = 10pF 0.5 Fall Time * tf max Measured at 2.4V – 0.4V; CL = 30pF 2.0 ns CK66_0:3 Clock Outputs Duty Cycle * dt Ratio of high pulse width to one clock period, measured at 1.5V 45 55 % Clock Skew * tsk(o) One clock output relative to another at 1.5V 250 ps Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 30pF 300 ps tr min Measured at 0.4V – 2.4V; CL = 10pF 0.5 Rise Time * tr max Measured at 0.4V – 2.4V; CL = 30pF 2.0 ns tf min Measured at 2.4V – 0.4V; CL = 10pF 0.5 Fall Time * tf max Measured at 2.4V – 0.4V; CL = 30pF 2.0 ns REF_0:1 Clock Outputs Duty Cycle * dt Ratio of high pulse width to one clock period, measured at 1.5V 45 55 % Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 20pF 1000 ps tr min Measured at 0.4V – 2.4V; CL = 10pF 1.0 Rise Time * tr max Measured at 0.4V – 2.4V; CL = 20pF 4.0 ns tf min Measured at 2.4V – 0.4V; CL = 10pF 1.0 Fall Time * tf max Measured at 2.4V – 0.4V; CL = 20pF 4.0 ns CK48_0:1 Clock Outputs Duty Cycle * dt Ratio of high pulse width to one clock period, measured at 1.5V 45 55 % Jitter, Period (peak-peak) * tj(∆P) From rising edge to rising edge at 1.5V, CL = 20pF 350 ps tr min Measured at 0.4V – 2.4V; CL = 10pF 1.0 Rise Time * tr max Measured at 0.4V – 2.4V; CL = 20pF 4.0 ns tf min Measured at 2.4V – 0.4V; CL = 10pF 1.0 Fall Time * tf max Measured at 2.4V – 0.4V; CL = 20pF 4.0 ns |
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