AD7674

Data Sheet

Rev. B | Page 8 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

48 47 46 45 44 43 42

41 40 39

38 37

35

CNVST

34

PD

33

RESET

30

DGND

31

RD

32

CS

36

AGND

29

BUSY

28

D17

27

D16

25

D14

26

D15

2

AVDD

3

MODE0

4

MODE1

7

IMPULSE

6

WARP

5

D0/OB/2C

1

AGND

8

D1/A0

9

D2/A1

10

D3

12

D5/DIVSCLK[1]

11

D4/DIVSCLK[0]

NOTES

1. NIC = NO INTERNAL CONNECTION.

2. DNC = DO NOT CONNECT.

13 14 15 16 17 18 19 20 21 22 23 24

AD7674

(Not to Scale)

TOP VIEW

Figure 4. 48-Lead LQFP Pin Configuration

NOTES

1. NIC = NO INTERNAL CONNECTION.

2. DNC = DO NOT CONNECT.

3. THE EXPOSED PAD IS INTERNALLY CONNECTED TO AGND. THIS

CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES.

HOWEVER, FOR INCREASED RELIABILITY OF THE SOLDER JOINTS, IT IS

RECOMMENDED THAT THE PAD BE SOLDERED TO THE ANALOG GROUND OF

THE SYSTEM.

1

2

3

AGND

CNVST

PD

4

RESET

5

CS

6

RD

7

DGND

AD7674

TOP VIEW

(Not to Scale)

25

D5/DIVSCLK[1]

26

D4/DIVSCLK[0]

27

D3

28

D2/A1

29

D1/A0

30

IMPULSE

31

WARP

32

D0/OB/2C

33

MODE1

34

MODE0

35

AVDD

36

AGND

8

BUSY

9

D17

10

D16

11

D15

12

D14

Figure 5. 48-Lead LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

1, 44

AGND

P

Analog Power Ground Pin.

2, 47

AVDD

P

Input Analog Power Pins. Nominally 5 V.

3

MODE0

DI

Data Output Interface Mode Selection.

4

MODE1

DI

Data Output Interface Mode Selection:

Interface Mode No.

MODE1

MODE0

Description

0

0

0

18-bit interface

1

0

1

16-bit interface

2

1

0

Byte interface

3

1

1

Serial interface

5

D0/OB/2C

DI/O

In Mode 0, 18-bit interface mode, this pin is Bit 0 of the parallel port data output bus and the data

coding is straight binary. In all other modes, this pin allows a choice of straight binary/binary twos

complement. When OB/2C is high, the digital output is straight binary; when low, the MSB is inverted,

resulting in a twos complement output from its internal shift register.

6

WARP

DI

Conversion Mode Selection. When this input is high and the IMPULSE pin is low, WARP selects the

fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be

applied to guarantee full specified accuracy. When low, full accuracy is maintained independent of

the minimum conversion rate.

7

IMPULSE

DI

Conversion Mode Selection. When this input is high and the WARP pin is low, IMPULSE selects a

reduced power mode. In this mode, the power dissipation is approximately proportional to the

sampling rate. When the WARP pin and the IMPULSE pin are low, the normal mode is selected.

8

D1/A0

DI/O

In Mode 0, 18-bit interface mode, this pin is Bit 1 of the parallel port data output bus. In all other

modes, this input pin controls the form in which data is output, as shown in Table 7.

9

D2/A1

DI/O

In Mode 0, 18-bit interface mode, or Mode 1, 16-bit interface mode, this pin is Bit 2 of the parallel port data

output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7.

10

D3

DO

In all modes except Mode 3, this output is used as Bit 3 of the parallel port data output bus. This pin is

always an output, regardless of the interface mode.